[外企内推]Principal Verification Engineer

bestgrace

简历请发bestgrace@qq.com  qq:2043753191



Job Title:

Sr. Staff / Principal Verification Engineer

  

Job Description:

As a core member of a SOC development team, primary responsibility will be verification environment development and verification planning and execution. Lead a verification group to accomplish SOC project verification tasks.  


Summary of Duties/Responsibilities:

·            SOC verification requirements analysis and planning

·            Architect and build OVM/UVM based test environment for complex IP and SOC full chip verification

·            Create test plan, and lead the verification organization to implement the verification tasks

·            Design coverage metrics and verification reporting system

·            Coordinate debug efforts to achieve IPs and full chip functionality

·            Documentation of verification, organize/participate in verification/design reviews. Drive verification methodology improvement

  

Job Requirements:

·            Excellent English and Mandarin skills

·            Takes initiative and sets high goals, smart and confident

·            Self starter & ability to work in a team environment as an individual contributor

·            Tracking record of planning and delivering successful verification projects

·            Expert in advanced verification methodology, like OVM, VMM

·            Ability to test silicon using logic analyzers, oscilloscopes, and other common laboratory equipment is a plus.

·            Thoroughly understand SOC development flow, solid knowledge of semiconductor technology

·            Familiar with popular industry protocols, including AHB, USB, I2C, UART, Ethernet, etc.

  

Education & Work Experience:

·         8+ years of verification environment development & SOC verification

·         2+  years of team/project management experience;

·         Expert in System Verilog and OVM or VMM verification methodology

·         Proficiency in Perl, Tcl, Tk, C/C++, Verilog, System Verilog languages

·         Tracking recording of successful SOC product delivery

·         Master's Degree or above in EE/CE

  

Benefits:

·         Competitive salary

·         Stock options

·         Excellent medical insurance plan

·         New product design bonus

·         Extensive training programs covering technology / management skills

  

Location:

Shanghai, China