[猎头]IC设计/验证工程师 要求硕士 至少2年经验

bestgrace

PHYSICAL DESIGN ENGINEER

RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of Graphic
s processors, integrated chipsets and other ASICs targeted at the desktop, lap
top, workstation, set-top box and home networking markets
- Participating in the efforts in establishing CAD and physical design methodo
logies, flow automation, chip floorplan, power/clock distribution, chip assemb
ly and P&R, timing closure
- Working on static timing analysis, power and noise analysis and back-end ver
ification across multiple projects

MINIMUM REQUIREMENTS:
- BSEE, MSEE preferred
- 2+ years of experience in large VLSI physical design implementation on 0.15u
, 0.13u, 90nm, or 65nm technology
- Successful track record of delivering products to production is a must.
- Understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drive
rs
- Prior experience in Timing closure, clock/power Distribution and analysis, R
C Extraction and correlation, place and route and tapeout issues
- Working knowledge of deep sub-micron routing issues as they relate to power
and timing
- Circuit level comprehension of time critical paths, and spice experience a p
lus
- Should be a power user of P&R and timing analysis CAD tools from Synopsys (A
stro/PC/dc_shell/pt_shell/STAR-RC), CADence (FE/Nanoroute), Sequence (Physical
Studio) or Magma
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred


GPU-ASIC-Physical Design Engineer

As a senior member of our ASIC-PD team, you'll be working on streamlining the
chip infrastructure process across product designs, focusing on such tasks as
clocks/timing/convergence/design for test and scripting of flows. You’ll be f
ocusing on full chip layout planning (partitioning, planning clock distributio
n and other structure, methodology), partition/full chip timing closure (prime
time scripts, other tools, etc) and gate-level design of high-speed logic

RESPONSIBILITIES:
- Work in conjunction with Place and Route Engineers to achieve timing closure
for both partition level and full chip level
- Develop and enhance entire timing flow from Frontend (pre-layout) to backend
(post-layout) at both chip and block level.
- Develop custom timing scripts using tcl/primetime for clock skew analysis, s
pecial circuits such as clock dividers, core logic <-> IO macros interfaces su
ch as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Chip level Integration
- Develop flow to physically partition and floorplan the entire chip.
- Develop and dc-shell scripts for performing ECO's.

MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- Above 3 years of relevant ASIC design experience ideally with a focus in tim
ing
- Excellent written and verbal communication skills in English
- Ability to multiplex many issues, set priorities, and work in a team environ
ment
- Keep up to date with leading edge technologies

ASIC Verification Engineer

RESPONSIBILITIES:
- Develop and maintain verification environment at both full chip & unit level
- Develop and execute verification plan
- Develop BFM
- Code/functional coverage analysis
- Responsible for running both RTL & gate level simulation

MINIMUM REQUIREMENTS:
- BSEE/MSEE/BSCS/MSCS with 3+ years of experience in digital circuit/ASIC veri
fication
- Possess knowledge in at least one of the below areas
&#8226; HDCP/TMDS/LVDS/DisplayPort
&#8226; Blending, color space conversion
&#8226; Image up and down sampling
- Strong problem solving and analytical skills
- Must be proficient in Verilog HDL
- Must be strong in Perl programming, or strong in Python/Ruby programming
- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)
- Working knowledge in C/C++, Makefile
- Verilog PLI experience is a plus

Principal Consultant & General Manager @ Hi-Talent Consulting Co. , Ltd.
上海芯相会企业管理咨询有限公司
E-Mail: bestgrace@qq.com
QQ: 2043753191
新浪blog: http://blog.sina.com.cn/u/1767088102

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