Cadence SH 招聘Leader PV Design Engineer

艾清别诺

面向对象是：应届博士生，或者往届硕士生

Leader PV Design Engineer

Job description:

1.
As an Encounterproduct validation engineer, he/she will contribute to overall Encounterquality/stability and usability,  enable designs easier to finish designtiming closure and chip finishing.

2.
Need to rundifferent designs from placement/cts/optimization to final SI timing closure,need to look at those timing degradations and analysis the reason, whetherplacement is not good, or optimization insert unreasonable buffers, or routingpattern is detour, etc. Also need to analysis those max_tran/max_cap/DRC/powerissues.

3.
Need to take newdesigns to add into regression suite. By given library and RTL netlist, she/hecan to create floorplan, create powerplan, go through APR flow to achieve DRCclean and timing closure, to get reasonable Performance/Power/Area metric, justlike taping out designs.

4.
Can explore newflows or methodology to improve timing closure efficiency, and give customersupport.

Position requirements:

1. Ph.D， or MSwith 2 year work experience.

2. Good at STA. Know aboutplace, routing, cts, optimization and SI analysis.

3. Know about RTL synthesis

4. Good at unix scripts, cshell.Perl is a plus

5. Strong ability in analysis and solving issues, strongability in facing difficulty and challenges. Proactive in work.

6.Good English skill, communication skill and good team work.

有意者请发简历到 xiulingl@cadence.com,谢谢