AMD(上海)SOC Team急招

amd_srdc

AMD(上海) SOC Team近期有数个Junior，Senior，Staff以及更高level的职位空缺招聘，感兴趣的同学可与我联系( mail : amd_cdc@163.com  QQ:1756384832)，team内部推荐成功率会更高些哦。
职位：

1.SOC Integration Engineer : 主要涉及Synthesis/STA/LEC/MVRC/CDC/GCA等，要求一定的脚本能力(perl,shell,tcl...)。如果对上述一个或多个领域熟悉并且感兴趣的同学可以来尝试下。

2.SOC DV Engineer : 主要涉及SOC chip level的verification已经Emulation。

具体JD：
a）SOC Integration Engineer：
The candidate is preferred to be MSEE or BSEE with several years experience indigital ASIC/SOC design engineering.
The candidate should have deep understanding on ASIC/SOC design flow and mustbe proficient in some following skill sets:
1. RTL(verilog) coding and style checking
2. Scripts based on makefile, perl, TCL or csh/tcsh
3. Clock-domain-cross checking
4. Logic synthesis
5. Static timing analysis
6. Logic equivalency checking
7. Top level integration, pad-ring design

b)SOC DV Engineer:
The candidate will be employed in dGPU SoC level verification.
Key Job Functions:
- Understand the architecture and functionality of the chip
- Compose test plan and validation vectors to ensure functional completeness
- Develop verification environments for standalone unit testing and enhance/usethe automated regression infrastructure setup for full chip functionalverification.
- Help debug and correct functional errors in the design blocks, using logicabstraction, simulation and debug tools, based on good understanding of thearchitectural
specification, RTL and/ordevice level design of the block.
- Be responsible to mentor and coach the team for greater technical depth inFunctional areas as well as the verification methodology improvement and Infrastructureenhancements to support the design environment
Preferred Experience:
- Major in EE, CS or related with 2+ years working experiences
- Should be versatile in any one of the high level verification flow such asSV,VMM,VERA,OVM etc as well as knowledge of industry standard tools forverification
- Needs to have better understanding of Verification methodology and concepts.
- Should have good understanding of Pre-Silicon design process fromArchitecture, Design, Synthesis and Gate level Implementation till Tapeoutrelease.
- Should have excellent communication skills (both written and oral) and shouldbe able to participate cross functional engineering teams geographically.
- Familiar with Linux Environment (including shell scripting and linux gnutools)
- Proficient programming knowledge on Verilog,C++
- Knowledge on UPF based verification is a plus
- Design for verification (assertion based design strategies, code coverage,functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Strong problem solving skills

fl550780

有低的职位么，应届生要不

wangjunweiair

顶一个呵呵

amd_srdc

回复 2# fl550780


    应届生只能走校招的通道哦

amd_srdc

Up

wakering

Great position ,I want to apply for ~

amd_srdc

有兴趣的同学，可以把简历发来哦

amd_srdc

up up up