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上海IC verification验证工程师招聘,工作经验两年以上即可~ 欢迎资深的应聘者
1、UFS unit flash storage
2、USB
3、Emmc SD
简历发送到 1305033340@qq.com 或者 candice.zhang@yiri-intl.com 。
也可加QQ:1305033340 沟通公司具体组织架构,面试流程,面试细节等详细信息~
The candidate must have: 1.
deep understanding on ASIC/SOC designflow 2.
Excellent knowledge of design verification methodology,such as VMM or OVM and UVM. 3.
Solid experiences with
simulation model creation and thetestbench build 4.
Strong RTL coding with Verilog 5.
Strong SystemVerilog experiences. 6.
Strong C/C++ software developmentexperiences 7.
Begood at scripting language, such as Perl, C shell, Ruby, and Makefile. It is amust that the candidate has one or more of the followingexperience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus,USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash hostcontroller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCIbus, low power design, clock generation and control, SD/eMMC host controller,SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs(I2S/I2C/UART), Ethernet, JTAG, etc. The candidate is expected to exhibit goodverbal and written communication skills in both Chinese and English, specializedknowledge plus broad technical knowledge that facilitates integrative thinking,, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problemsand decision-making on critical technical areas Hands-on lab experience is another plus, able tounderstand and/or use the use scopes, logic analyzers, has knowledge or skillof board-level lab debugging. Responsibility: The successful candidate will work with teammembers and apply current functional verification techniques to perform andimprove pre-silicon verification quality and product Time to Market forSouthbridge design. The candidate will provide the technical leadership to theDV team for the new Southbridge project. He/She should be able to workindependently on various DV tasks and providing technical guidance to the DVteam. The candidate would involve technically in the porting/creation of the DVenvironment for the new design, block and chip level test plan creation andimplementation, coverage analysis, and regression cleanup.
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