上海徐汇招聘dft和后端工程师

2492202119

qq:2492202119 欢迎联系

美国硅谷工程师创办的外商独资企业，主要提供Fabless ASIC芯片设计技术服务。我们拥有世界一流芯片设计的团队，多次为海外公司成功地提供了基于45纳米µm、低功耗工艺的大型高端芯片的设计服务。
高尖端的科技是您通往事业之路的桥梁，理想的工作环境是您展示才华的舞台，现招聘致力于芯片设计的卓越人才加入我们

DFT Division
职位性质：不限
外语要求：无
职称要求：不限
工资待遇：面议
专业要求：不限
工作经验：一年以上
学历要求：本科及以上
招聘人数：若干人

职位描述
Responsibilities: Synthesis: Use DC (Design Compiler), ACS (Advanced Chip Synthesis), and PC (Physical Compiler) for chip synthesis either from RTL code or Gate level netlist; Static Timing analysis and Formal verification: Perform timing analysis and timing optimization; Run formal verification after each ECO and timing optimization; DFT design: Scan chain insertion; JTAG/Boundary scan insertion; NAND tree insertion; Memory BIST insertion; Logic BIST insertion; Test pattern generation and simulation: ATPG test vector generation and pattern simulation; Fault grading test vector generation; Memory BIST simulation; JTAG/NAND tree simulation; Test vectorl format conversion and provide all test related patterns to test and product engineers; Requirements: BS, MS preferred; 0-3 years working experience on chip integration; Strong Logic design and Semiconductor device physic background; Good English in both written and spoken.
Physical Design Manager
职位性质：不限
外语要求：无
职称要求：不限
工资待遇：面议
专业要求：不限
工作经验：五年以上
学历要求：大专及以上
招聘人数：若干人

职位描述
Responsible for all aspects of physical design and implementation of integrated circuits and other ASIC. Responsibilities include: Participating in the efforts in establishing CAD and physical design methodologies; Focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology); Chip floor plan; Power/clock distribution; Chip assembly and P&R; Timing closure; Power and noise analysis; Back-end verification across multiple projects; Requirements: BSEE 5+years,MSEE 3+years experience in large VLSI physical design implementation; Successful track record of delivering products to production is a must; Understanding of custom Macro blocks such as RAMs, PLLs, high-speed IO drivers; Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues; Working knowledge of deep sub-micron routing issues as they relate to power and timing; Circuit level comprehension of time critical paths. Spice experience a plus; Should be a power user of Apollo/Astro for routing, PhysOpt (Physical Compiler) for placement, PrimeTime for Timing Verification, dc_shell etc.
PR Engineers
职位性质：不限
外语要求：无
职称要求：不限
工资待遇：面议
专业要求：不限
工作经验：一年以上
学历要求：本科及以上
招聘人数：若干人

职位描述
Responsibilities: Layout database creation : layout library and Milkyway database creation; Initial floorplan : Initial chip or subchip level floorplan; Place & Route: Perform cells placement; Perform global route and detail route; DRC/LVS corrections; Layout script creation: Create script to perform layout modification; Create Apollo scheme file to maintain and update Apollo database; Layout modification: Follow signal integration report to perform necessary modification; Requirements: Bachelor Degree or higher in EE major; 0-3 years P&R working experience; Knowledge about Solaris/Unix/Linux operating system; Good command of English in both written and oral format.
JD: 1. lead soc design team; 2. be able to interface &communicate with internal colleague and external customer; 3. be able to provide design guidance and instruction to engineers; 4. be able to hands-on work on Top level/block level physical design independent

JR: 1. minimum of 5 yrs of working experience; 2. master degree of EE or related field is preferred; 3. team leader or functional leader experience is preferred; 4. familiar with either Synopsys or Cadence design flow and EDA tools; 5. fluent in both Chinese and English
staff engineer

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qq:2492202119 欢迎联系

美国硅谷工程师创办的外商独资企业，主要提供Fabless ASIC芯片设计技术服务。我 ...
2492202119 发表于 2013-6-17 15:30

                               
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