Cadence SH 招聘Product Engineer & Principal/Lead PV Design Engineer

kengteng

Cadence SH 招聘Product Engineer &
Principal/Lead PV Design Engineer

If you have interest, PLS send your CVto zhangyl@cadence.com

Title: ProductEngineer- PVS

Position Description:

TheProduct Engineering team works with Customers and foundries, R&D, Marketing,and the Field Applications Engineers to create products that address the uniqueand complex needs of our customers. A Physical Verification Product Engineerprovides in-depth technical expertise in writing Physical Verification ruledecks (i.e. DRC, ERC, FILL and LVS) and the usage of Physical Verificationtools throughout physical implementation and signoff verification cycles.

Responsibilities:

DevelopPhysical Verification rule decks (i.e. DRC, ERC, FILL and LVS)

Setupefficient flows to improve rule deck development quality and productperformance.

Runexpert-level benchmarks and solve complex customer problems.

Work withthe RD, field, customers and foundries to identify and define productrequirement and enhancement

Position Requirements:         

Knowledgeof developing rule decks for commercial physical verification tools (e.g. PVS,Calibre, Hercules, Dracula, Assura, etc.) is required.

Experiencein the following areas:

- DRC,includes density, antenna, etc.

- LVS,includes device extraction, parameter measurement, connect/stamp sequences,short isolation, etc.

-Knowledge of netlist formats SPICE, CDL, Verilog, etc.

- DFM,includes yield analysis, via insertion, OPC, FILL, etc.

Experiencewith layout implementation tools (e.g. Virtuoso, DesignREV, ICStation, etc.)for the creation of qualification cells is required.

Knowledgeof automating test suites for the qualification of rule decks is a plus.

Programmingof Tcl, Perl, and Skill are a plus

EDUCATION:BS or MS in Electrical Engineering.

Job Title:
Principal/Lead PV Design Engineer

Jobdescription:

1.
As an Encounter product validationengineer, he/she will contribute to overall Encounter quality/stability andusability, enable designs easier to finish design timing closure and chipfinishing.

2.
Need to run different designs fromplacement/cts/optimization to final SI timing closure, need to look at thosetiming degradations and analysis the reason, whether placement is not good, oroptimization insert unreasonable buffers, or routing pattern is detour, etc.Also need to analysis those max_tran/max_cap/DRC/power issues.

3.
Need to take new designs to add intoregression suite. By given library and RTL netlist, she/he need to createfloorplan, create powerplan, go through APR flow to achieve DRC clean andtiming closure, to get reasonable Performance/Power/Area metric, just liketaping out designs.

4.
Can explore new flows or methodologyto improve timing closure efficiency, and give customer support.

Position requirements:

1. Ph.D or excellent MS which isfamiliar with APR flow.

2. Good at STA. Know about place,routing, cts, optimization and SI analysis is a plus.

3. Know about RTL synthesis

4. Good at unix scripts, cshell. Perlis a plus

5. Strong ability in analysis andsolving issues, strong ability in facing difficulty and challenges. Proactivein work.

6. Good English skill, communication skill and good team work.