nvidia 上海招聘-ASIC/DFT/physical design/verif

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Senior ASICDesign Engineer

Responsibilities:

TheASIC design engineer is expected to co-work with architect to definearchitecture/micro-architecture, do RTL implementation and set up projectmilestones and drive design & verification progress and track projectstatus.

MinimumRequirement:

-BS/MS in electrical/computer engineering and related.

-At least 4+ year’s experience in ASIC design/verification.

-Strong design/implementation skills in Verilog. Solid understanding intiming/power optimization skills of digital design.

-Familiar with ASIC design flow such as micro-arch spec definition and testplandocumentation and code coverage and function coverage strategy.

-Strong sense of design timing and area and clock skew issue.

-Strong Perl/Csh scripting skills.

-Fluent English (both written and spoken) and excellent communication skills

-Demonstrated ability to work independently as well as in a multi-disciplinarygroup environment

-Familiar with LCD/LVDS/DisplayPort/HDMI, vertical/horizontal scalar and colorspace is a big plus

ASIC
Design/VerificationEngineer

RESPONSIBILITIES:

-RTL design, verification, synthesis for various low power control logic in GPUchips.

-Develop and maintain verification environment at both full chip & unitlevel

-Code/functional coverage analysis

-Responsible for running both RTL & gate level simulation

-Develop testing and regression methodologies

-Develop/maintain/enhance environment tools/scripts/makefiles

MINIMUMREQUIREMENTS:

-BSEE/MSEE/BSCS/MSCS with 2+~5+ years of experience in ASIC design or verification

-Proficient in Verilog HDL

-Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)

-Working knowledge in C/C++, Makefile

-Must have strong programming skills in one or more scripting languages: TCL,Perl, Python

-Knowledge in one of the below areas is a big plus

+ UVM/VMM experience

+ Low powerdesign/verification experience (Multi-Voltage, power gating, UPF/APF and etc.)

+ ARM based SoCverification experience

+ AHB/AXIarchitecture

+ Embedded OS

SOC Verification Engineer(Power)

RESPONSIBILITIES:

-verification for
power managementunit/global power feature of SOC chips.

-Develop and maintain verification environment for cluster level

-Code/functional coverage analysis

-Develop feature testplan according to feature description

-Develop/maintain/enhance environment tools/scripts/makefiles

MINIMUMREQUIREMENTS:

-BSEE/MSEE/BSCS/MSCS with 3+/5+ years of experience in ASIC design orverification

-Proficient in Verilog HDL

-Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)

-Working knowledge in C/C++, Makefile

-Knowledge in one of the below areas is a big plus

+ Strong programming skills in one or morescripting languages: TCL, Perl, Python

+ Low power design/verificationexperience (Multi-Voltage, power gating, UPF/APF and etc.)

+ ARM based SoCverification experience

+ UVM/VMM experience

Sr. ASIC VerificationEngineer (Clock)

Job Description/Qualifications:

RESPONSIBILITIES:

- ASIC Verification for the most complex GPU clock designat both unit level and chip level.

- Debug and fix SOC level issues

- Maintain/Develop the working environment

- Working closely with various unit teams to solve clockissues.

- Support backend team’s work as the bridge betweenfrontend and backend

MINIMUMREQUIREMENTS:

- Experience in both unit level and chip level verification.

- Good at debugging and problem solving.

- Experience in verification methodology development.

- Programming skills in C and PERL.

- Familiar with clock logic is preferred, such as PLL,clock dividers, trimmers, clock switches, etc.

- Good communication skills, creative, and proactive.

- The ideal candidate will be familiar with all aspectsof the frontend ASIC design flow including RTL design, verification, synthesis,and timing analysis

- BS in Electronic Engineering, MS preferred.

DFT enginner

Responsibilities:

·
Responsible for DFT implementation including test modecontrollers, Memory BIST/Repair and JTAG based on DFT plan.

·
Responsible for scan insertion, ATPG and post silicon validation.

·
Responsible for DFT logic and pattern verification.

·
Responsible for ATE chip bringup and failure analysis.

Minimum Requirement:

·
BSEE required, MSEE preferred.  

·
2+ years of experience in DFT/design field

·
Strong logic Design and verification background withexperience in STA.

·
Must possess a strong knowledge of DFT including scan, ATPG, Test Compression,JTAG and BIST.

·
Programming in Perl, tcl and C/C++ is a plus

·
Good Englisth communication skills

·
Self-motivated and good team player

GPU ASICPhysical Design engineer

As a senior member of our ASIC-PD team, you'll be working on streamlining thechip infrastructure process across product designs, focusing on full chiplayout planning (partitioning, planning clock distribution and other structure,methodology), partition/full chip timing closure (primetime scripts, othertools, etc) and gate-level design of high-speed logic

RESPONSIBILITIES:

-Chip integration and netlist generation

-Synthesis,Formal verification, netlist quality check

-Work in conjunction with Place and Route Engineers to achieve timing closurefor both partition level and full chip level
- Develop and enhance entire timing flow from frontend (pre-layout) to backend(post-layout) at both chip and block level.
- Develop custom timing scripts using tcl/primetime for clock skew analysis,special circuits such as clock dividers, core logic <-> IO macrosinterfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Develop flow to physically partition and floorplan the entire chip.
- Develop scripts for performing ECO's.

MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- Above 3 years of relevant ASIC experience ideally with a focus in the chipintegration /synthesis/formal and timing closure

- Excellentscripts skills

- Excellentwritten and verbal communication skills in English

- Ability tomultiplex many issues, set priorities, and work in a team environment

- Keep up todate with leading edge technologies

nvidia内部员工referral

lgao@nvidia.com

欢迎邮件咨询

sailen

怎么都是要工作经验的啊，有没有要应届生的啊，，，我在某IC公司实习一年算不算工作经验啊，求内推。

pastchen

同2楼情况的要不要阿