New layout design for submicron CMOS output transistors

layes

New layout design for submicron CMOS output transistors
to improve driving capability and ESD robustness

cheny1982

zhanweisu27

看看,,,这也是比较常用的东西

ahhuh

good for learning, thank you

semico_ljj

还是建议楼主贴个介绍出来吧，方便大家，也方便自己！

semico_ljj

Abstract
New layout design to e€ectively reduce the layout area of CMOS output transistors but with higher driving
capability and better ESD reliability is proposed. The output transistors of large device dimensions are assembled by
a plurality of the basic layout cells, which have the square, hexagonal or octagonal shapes. The output transistors
realized by these new layout styles have more symmetrical device structures, which can be more uniformly triggered
during the ESD-stress events. With theoretical calculation and experimental veri®cation, both higher output driving/
sinking current and stronger ESD robustness of CMOS output bu€ers can be practically achieved by the proposed
new layout styles within a smaller layout area in the non-silicided bulk CMOS process. The output transistors
assembled by a plurality of the proposed layout cells also have a lower gate resistance and a smaller drain
capacitance than that realized by the traditional ®nger-type layout. # 1999 Elsevier Science Ltd. All rights reserved

semico_ljj

是我久仰的M.-D. Ker的论文！呵呵！

ahhuh

new technique, want to have a look

cheny1982

cheny1982