They do the same things but verilog is mainly for low level and VHDL is for aliitle higher abstract designs. Verilog syntaxes are like C so learning it is alittle simpler that VHDL. I suggest to learn first verilog then Systemverilog then Systemc. SystemC is more harder and synthesis from it is alittle costly.
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发表于 2012-10-13 06:50:16
