ansoft designer如何导入verilog-a进行仿真？

feitengyu

ansoft designer如何导入verilog-a进行仿真？
哪位知道如何弄？按照help给的一个 电阻例子的步骤 还是出错 不能使用
不知道问题出在什么地方

按照help的简单描述

首先建立一个原理图元件模型，然后建立元件模型，链接va文件

但是发现仿真还是不对

feitengyu

*Global - Messages
  [warning] The application could not resolve the IP address of this machine: remote analysis and remote distributed analysis will not work.
  [warning] Left-alt + shift is currently used by the system to toggle the input language. It is also used in some portions of this application, which may cause the input language to change unexpectedly.
Project4 (F:/systest/)
  Circuit1
    [info] Nexxim simulation will use local parameter scoping. To change this option, please go to Tools>Options>Nexxim Circuit Options. (7:41:56 下午  八月 09, 2012)
    [error] Component 'RES_Verilog', ID '24':  Pin number in node reference must be between 0 and one less than the number of component terminals, e.g., %0, simulator lang=spectre\n ahdl_include @file \n R@ID \(%0 %1\)@SubcktName R=@R \n simulator lang=nexxim (7:41:56 下午  八月 09, 2012)
    [info] Analyzing...F:/systest/Project4.adsnresults/Circuit1/temp/DV10_S8_V107.cir (7:41:56 下午  八月 09, 2012)
    [info] (status): Nexxim version: 6.0.0 WIN32, build time: Oct 14 2011, 06:41:04  (7:41:56 下午  八月 09, 2012)
    [error] parser(error): f:/systest/project4.adsnresults/circuit1/temp/dv10_s8_v107.cir:26: Parse Error (7:41:56 下午  八月 09, 2012)
    [error] models:resistor(error): R24 - r=@SubcktName not valid (7:41:57 下午  八月 09, 2012)
    [error] models:resistor(error): R24 - R=@R not valid (7:41:57 下午  八月 09, 2012)
    [warning] models:resistor(warning): R24 - Resistance value less than RESMIN, resetting value to 1e-005 (7:41:57 下午  八月 09, 2012)
    [error] (error): Error found during loading: analysis aborted for F:/systest/Project4.adsnresults/Circuit1/temp/DV10_S8_V107.cir (7:41:57 下午  八月 09, 2012)
    [info] (status): Start Time:  08/09/2012 19:41:56, Host ICZHAOHB, Nexxim Version 7.0.0 (7:41:57 下午  八月 09, 2012)
    [info] (status): Total 0:00:01   End Time:  08/09/2012 19:41:57 (7:41:57 下午  八月 09, 2012)
    [error] (error): Some or all simulation failed for F:/systest/Project4.adsnresults/Circuit1/temp/DV10_S8_V107.cir (7:41:57 下午  八月 09, 2012)
    [info] Analyzing done.... (7:41:57 下午  八月 09, 2012)
  [info] Specified library cannot be found:  Verilog_Resistors (8:36:00 上午  八月 09, 2012)
  [warning] Definition 'verilog\Verilog_Resistors:RES_Verilog' in library Verilog\Verilog_Resistors has been modified. (8:42:50 上午  八月 09, 2012)
  [info] Specified library cannot be found:  Verilog_Resistors (7:39:36 下午  八月 09, 2012)
  [warning] Definition 'verilog\Verilog_Resistors:RES_Verilog' in library Verilog\Verilog_Resistors has been modified. (7:40:42 下午  八月 09, 2012)

xiayngg

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amirjon

thanks dear ...............

baggio_bupt

谢谢~~~~

chenyuanzhi1989

thanks dear ...............