Understanding Signal Integrity

pumpkin

CHAPTER 1
Introduction to Signal Integrity 1
1.1 What Is Signal Integrity? 1
1.2 The Importance of Signal Integrity: The First Transatlantic
Telegraph Cable 1
1.3 What Is a Pulse? 3
1.4 Time and Frequency Domains 4
1.4.1 Line Spectrums 4
1.4.2 Recreating a Pulse with Sine Waves 4
1.4.3 Why Does the Frequency Domain Matter to Signal
Integrity Engineers? 5
1.4.4 Upper Bandwidth 7
1.5 Power Integrity and Simultaneous Switching Noise 8
1.5.1 What Is Simultaneous Switching Noise? 8
1.6 What Is the Dielectric Constant and Loss Tangent? 9
1.7 Main Points 10
References
CHAPTER 2
The Signal Integrity Process 13
2.1 Introduction 13
2.2 Why Perform a Signal Integrity Analysis? 13
2.3 What Is a Typical Signal Integrity Workfl ow? 14
2.4 Signal Integrity Worst-Case Analysis 16
2.4.1 Silicon Worst-Case I/O Models 17
2.4.2 What Combination of Environmental Effects Are Worst Case? 17
2.4.3 Using SI Analysis Results During Debug 18
2.4.4 Electrical Overstresses 19
2.5 Main Points 19
References 20
CHAPTER 3
Signal Integrity CAD and Models 21
3.1 Introduction 21
3.2 I/O Models 21
3.2.1 What Are Transistor Level Models? 21
3.2.2 What Are IBIS Models? 22
3.3 Modeling Transmission Lines 23
3.4 S-Parameters 24
3.4.1 What Are S-Parameters? 24
3.4.2 What Is Insertion Loss? 24
3.4.3 What Is Refl ection Loss? 26
3.4.4 What Are Touchstone Files? 26
3.5 Field Solvers 26
3.5.1 What Are 2D Field Solvers? 26
3.5.2 What Are 3D Field Solvers? 27
3.6 Main Points 28
References 28
CHAPTER 4
Printed Test and Evaluation Boards 31
4.1 Introduction 31
4.2 Test Boards 31
4.2.1 Test Boards as a Chip Debug Platform 32
4.2.2 Margining Power Supply 33
4.2.3 Testing Decoupling Capacitor Effi cacy 33
4.2.4 Testing Sensitivity to Clock Quality 33
4.3 Evaluation Boards 33
4.4 Roll of the Printed Circuit Layout Shop 34
4.5 Fabricating and Assembling the Board 35
4.6 Alternative Methods for Design and Fabrication 35
4.7 Main Points 36
References 36
CHAPTER 5
Printed Circuit Board Construction 37
5.1 Introduction 37
5.2 How Is a Multilayer Circuit Board Constructed? 37
5.2.1 How Are Connections Made Between Layers? 37
5.2.2 What Is the Via Aspect Ratio? 39
5.3 What Is the Signifi cance of Calling a Circuit Board “FR4”? 39
5.3.1 Why Is There Such Variability in Dk Between Laminate
Manufacturers? 40
5.3.2 Why Is the Same Board Produced Differently by Various Fab Shops? 41
5.3.3 What Are Some Alternatives to FR4? 41
5.4 Circuit Board Traces 42
5.4.1 Microstrip 43
5.4.2 Stripline 43
5.4.3 What Is a Mil and What Does a Trace Thickness in Ounces Mean? 43
5.4.4 What Copper Types Are Used to Form Traces and What Are Their
Characteristics? 45
5.4.5 What Is Surface Roughness and What Are Typical Values? 45
5.4.6 Are Traces Rectangular? 46
5.5 Main Points 46
Problems 47
References 48
CHAPTER 6
Transmission Line Fundamentals 49
6.1 Introduction 49
6.2 What Is a Transmission Line? 49
6.2.1 What Is the Signal Return Path? 49
6.3 Circuit Model of a Transmission Line 50
6.4 Impedance and Delay 51
6.4.1 Units and Electrical Length 52
6.5 How Does a Signal Travel Down the Line? 52
6.5.1 What Voltage Gets Launched Down a Transmission Line? 54
6.6 How Does the Current in the Return Path Behave? 55
6.6.1 How Does Current Flow in Return Paths That Are Not Ground? 55
6.6.2 What Is the Behavior When One Return Path Is a Related
Power Plane? 56
6.6.3 How Does the Return Current Flow When the Power Supply
Is Not the Signaling Voltage? 57
6.7 When Does a Conductor, Via, or Connector Pin Act Like a
Transmission Line? 58
6.7.1 Why Does the Signal Rise Time Matter But Not the Pulse Width? 59
6.7.2 Why Does Propagation Delay Time Depend on the Line Length,
But Impedance Does Not? 59
6.8 Main Points 59
Problems 60
References 61
CHAPTER 7
Understanding Microstrip and Stripline Transmission Lines 63
7.1 Introduction 63
7.2 DC Resistance and Resistivity 63
7.3 Stripline and Microstrip Capacitance 64
7.3.1 What Is the Effective Dielectric Constant? 65
7.3.2 What Are the Differences Between Microstrip and Stripline
Capacitances? 66
7.3.3 How Does Frequency Alter the Loss Tangent? 67
7.3.4 What Is Conductance and How Is It Determined? 67
7.4 Stripline and Microstrip Inductance 68
7.5 How Does the Skin Effect Change the Trace’s Resistance? 69
7.5.1 What Is the Proximity Effect? 69
7.6 How Does the Skin Effect Change the Inductance? 71
7.7 Understanding Stripline and Microstrip Impedance 71
7.8 Understanding Stripline and Microstrip Propagation Delay Time 73
7.8.1 How Do the Dielectric and Effective Dielectric Constants Affect
Delay Time? 73
7.8.2 How Sensitive Is Delay Time to Changes in the Dielectric Constant? 74
7.9 Main Points 74
Problems 76
References 76
CHAPTER 8
Signal Loss and the Effects of Circuit Board Physical Factors 79
8.1 Introduction 79
8.2 What Are Transmission Line Loss and Attenuation? 79
8.2.1 What Effects Do Losses Have on Signals? 79
8.2.2 How Is Loss Specifi ed? 80
8.2.3 Converting Between Decibels and Percentage Loss 81
8.3 What Creates Transmission Line Loss and How Is It Characterized? 81
8.3.1 Loss Differences Between Microstrip and Stripline Traces 82
8.4 How Do Impedance and Loop Resistance Affect Conductor Loss? 83
8.4.1 How Does Surface Roughness Increase Conductor Loss? 84
8.4.2 Surface Roughness in Perspective 85
8.4.3 What Can Be Done to Reduce Conductor Losses? 85
8.5 Understanding Dielectric Losses 86
8.5.1 Differences in Dielectric Losses Between Stripline and Microstrip 87
8.5.2 Effects of Temperature and Moisture 87
8.5.3 What Can Be Done to Reduce Dielectric Losses? 88
8.6 Summary of Signal Loss and Distortion Characteristics 88
8.7 Effects of Resin Content and Glass Weave on Delay Time and
Impedance 89
8.8 Effects of Trace Shape 89
8.9 Main Points 89
Problems 90
References 91
CHAPTER 9
Understanding Trace-to-Trace Coupling 93
9.1 Introduction 93
9.2 Understanding Mutual Capacitance and Inductance 93
9.2.1 What Are the Capacitance and Inductance Matrices? 93
9.2.2 Why Do Some Field Solvers Report Capacitances with Negative
Numbers? 95
9.3 How Does Switching Alter the Trace Inductance and Capacitance? 95
9.3.1 How Is the Capacitance Affected? 96
9.3.2 How Is the Inductance Affected? 97
9.4 What Effect Does Coupling Have on Impedance and Delay? 98
9.5 What Are Odd and Even Modes? 99
9.5.1 Can the Odd- and Even-Mode Equations Be Used with More
Than Two Traces? 101
9.5.2 Why Is the Even- and Odd-Mode Timing the Same for Stripline
But Not Microstrip? 101
9.5.3 By How Much Does the Even- and Odd-Mode Impedance Change? 102
9.6 What Are the Circuit Effects When Switching Causes the
Impedance to Change? 103
9.7 How Is Receiver Timing Affected by In- and Out-of-Phase Switching? 103
9.8 Main Points 105
Problems 105
References 106
CHAPTER 10
Understanding Crosstalk 107
10.1 Introduction 107
10.2 How Is Crosstalk Created and What Are Its Characteristics? 107
10.3 Far-End Crosstalk 109
10.3.1 Calculating FEXT 109
10.3.2 What Are Typical Kf Values? 111
10.3.3 FEXT Summary 112
10.4 Near-End Crosstalk 112
10.4.1 Calculating NEXT 112
10.4.2 What Are Typical Kb Values? 114
10.4.3 NEXT Summary 115
10.5 How Closely Do Calculation and Simulation Agree? 115
10.5.1 How Well Do 2D Field Solvers Agree? 116
10.6 Guard Traces 116
10.6.1 Connecting the Guard Trace 117
10.7 Main Points 117
Problems 119
References 121
CHAPTER 11
Understanding Signal Reflections 123
11.1 Introduction 123
11.2 How Are Refl ections Created? 123
11.2.1 A Physical Analogy for Transmission Line Refl ections 126
11.3 The Refl ection Coeffi cient 126
11.3.1 What Determines the Refl ection Coeffi cient Value? 126
11.4 How Do the Refl ected Waves Combine with the Incident Waves? 127
11.4.1 Difference Between the Response of a Pulse and a Step 127
11.5 What Is the Behavior When There Are Multiple Refl ections? 128
11.5.1 What Is the Behavior When There Are Many Pulses? 132
11.6 Reactive Discontinuities 132
11.7 Main Points 134
Problems 135
References 135
CHAPTER 12
Termination Strategies 137
12.1 Introduction 137
12.2 Source Series Termination 137
12.2.1 Selecting the Resistance Value 137
12.2.2 Effect of Driver Resistance 139
12.2.3 Power Savings 139
12.3 Parallel and Thevenin Termination 139
12.3.1 Selecting Vtt and Vterm 141
12.3.2 Thevenin Termination 142
12.3.3 Connecting Rterm Directly to Vdd or Ground 143
12.4 Diode Termination 143
12.4.1 Diode Types 144
12.5 AC Termination 145
12.6 Topologies 146
12.6.1 Single-Load Point-to-Point Termination 146
12.6.2 Multiple Load Point-to-Point Termination 148
12.7 Multidrop Lines 150
12.7.1 Response When Signal Rise Time Is Very Short 151
12.7.2 Response When Signal Rise Time Is Comparable to the
Transmission Line Delays 152
12.8 Stubs and Branches 154
12.8.1 Branches 155
12.9 Main Points 157
Problems 158
References 159
CHAPTER 13
Differential Signaling 161
13.1 Introduction 161
13.2 What Are the Electrical Characteristics of Differential Signaling? 162
13.2.1 How Is a Differential Pair Observed? 163
13.2.2 What Is an Eye Diagram? 163
13.2.3 What Is Intersymbol Interference? 164
13.2.4 How Are the Effects of Loss Corrected? 165
13.3 What Are the Electrical Characteristics of a Differential
Transmission Line? 165
13.3.1 Why Is the Differential Impedance Twice the Odd-Mode
Impedance? 166
13.4 How Are Differential Transmission Lines Terminated? 169
13.4.1 How Should a Diff-Pair Be Terminated When the Propagation
Is Not Fully Odd Mode? 170
13.4.2 What Prevents Creating Odd-Mode Signals? 172
13.5 How Are Differential Transmission Lines Created? 172
13.5.1 Manufacturing Trade-Offs Between Loosely and Tightly
Coupled Pairs 173
13.5.2 Electrical Trade-Offs Between Loosely and Tightly Coupled Pairs 174
13.6 What Are Some Suggested Diff-Pair Layout and Routing Rules? 174
13.6.1 Obtaining the Proper Differential Impedance 175
13.6.2 Signal Trace Between Diff-Pairs 176
13.6.3 Keeping Signal Traces Far Away from Diff-Pairs 176
13.6.4 Avoid Return Path Splits 177
13.6.5 Route on Same Layers 177
13.6.6 Minimize Layer Hopping 178
13.6.7 Use Differential Vias 178
13.6.8 Match Overall Trace Lengths 178
13.6.9 Match Lengths on Each Layer 178
13.6.10 Ensure That Noise Is Equally Coupled to Both Traces 179
13.7 Main Points 181
Problems 181
References 182
CHAPTER 14
Trace and Via Artwork Considerations for Signal Integrity 185
14.1 Introduction 185
14.2 Mitered Corners 185
14.3 Routing Near the Board Edge 187
14.4 Serpentine Traces 188
14.4.1 How Are Serpentine Delay Lines Modeled? 190
14.4.2 Effects of Corners 190
14.4.3 How Long Should the Segments Be? 190
14.4.4 Guard Traces 191
14.5 Vias 191
14.5.1 Via Circuit Model 191
14.5.2 What Factors Determine Via Capacitance? 192
14.5.3 What Factors Determine Via Inductance? 193
14.5.4 What Are the Effects of Different Antipad Diameters? 193
14.5.5 What Are Nonfunctional Pads? 193
14.5.6 Can the Via Impedance Be Adjusted? 194
14.5.7 What Are Differential Vias? 194
14.6 Main Points 195
References 195
CHAPTER 15
Identifying Common Signal Integrity Problems 199
15.1 Introduction 199
15.2 Questions to Ask When Reviewing PCB Stackup 199
15.3 Questions to Ask When Reviewing Crosstalk Simulations 201
15.4 Questions to Ask When Reviewing Signal Quality Simulations 202
15.5 Questions to Ask When Reviewing Prelayout Simulations 204
15.6 Questions to Ask When Reviewing Postlayout Simulations 205
15.7 Questions to Ask When Reviewing a Termination Strategy 206
15.8 Questions to Ask When Reviewing PCB Layout Design Rules 206
15.9 Questions to Ask When Reviewing ASIC Driver Selection Choices 206
References 207
CHAPTER 16
Solving Common Signal Integrity Problems 209
16.1 Introduction 209
16.2 Reducing Crosstalk 209
16.3 Reducing Refl ections 210
16.4 Reducing and Eliminating Simultaneous Switching Noise (SSN) 211
16.5 Improving Inadequate Timing Margins 211
16.6 Correcting Intersymbol Interference (ISI) 212
16.7 Steps to Take When Circuit Board Traces Are Too Lossy 213
16.8 Options to Reduce Circuit Board Thickness 213
16.9 Steps to Take When There Are Not Enough Routing Layers 214
16.10 Steps to Take When a Circuit Board Must Be Cost Reduced 215
16.11 Steps to Take When Data-Dependent Errors Are Causing System
Failures 216
References 216
CHAPTER 17
Calculating Trace and Plane Electrical Values 217
17.1 Introduction 217
17.2 How to Convert from Decibel Loss to Signal Swing 217
17.3 Estimating DC Resistance 218
17.4 Finding Inductance and Capacitance When the Physical Dimensions
Are Not Known 219
17.5 Finding Stripline Inductance and Capacitance When Impedance
Is Known 220
17.6 Finding Stripline Inductance and Capacitance When Trace Geometry
Is Known 220
17.7 Finding Microstrip Inductance and Capacitance When Trace
Geometry Is Known 221
xiii
17.7.1 Microstrip Inductance 221
17.7.2 Microstrip Capacitance 221
17.8 Estimating Inductance and Capacitance of a Plane 222
17.8.1 Inductance 222
17.8.2 Capacitance 223
17.9 Calculating Trace Loss from a Circuit Model 223
17.10 Calculating Stripline Loss from Trace Dimensions 224
17.10.1 Dielectric Loss 224
17.11 Calculating Microstrip Loss from Trace Dimensions 225
17.11.1 Dielectric Loss 225
17.12 Finding Stripline Impedance 226
17.13 Finding Exposed Microstrip Impedance 226
17.14 Finding Solder Mask Covered Microstrip Impedance 227
17.15 Wavelength 228
References 229
About the Author 231
Index 233

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