【上海】【通信芯片设计工程师】上海北欧通信芯片公司 高薪招聘

jamesyao007

科锐国际代招：上海（北欧）通信芯片公司招聘芯片设计类职位科锐代招：岗位名称：SOC芯片设计/验证/后端、模拟芯片设计（物理层软/硬件开发职位 -大量-北京-本文底）
工作地点：上海

客户公司描述：整合了众多豪门的半导体无线部门、无线微电子部门、无线部门以及中国TD产业进程上最重要的参与者和见证者。
为全球超过20亿的用户带来智能通信、手机娱乐、移动通信及宽带连接访问等服务及半导体产品公司。

POSITION:  DIGITAL DESIGN ENGINEER（芯片研发工程师-数字前端设计）  工作地：上海

JOB description：
As a Digital Design Engineer you are member of one or our PMU product development teams. You will be developing digital control circuits for innovative mixed signal high voltage (20 V) CMOS ICs. You fulfill an important role in the integration of these modules into PMUs (top-level design and simulations). The role will cover the full IC design cycle from specification through to testing of engineering samples.

1．Design & Development
Translating requirements (IP, IC) into implementation specifications
Development of digital IP (VHDL & Verilog coding, synthesis) and mixed signal IP (schematic level) taking into account all requirements(power usage, functionality, timing, size)
Together with test engineering making the designs industrial testable aiming for proper coverage and optimized test times (DFT)
aking care of configuration data management on IP and IC level and able to fulfill role as project integrator
Integration of top level mixed signal power management IC’s
Support project teams with debugging and finding solutions for products not performing to specification both on IP and IC level
2. Verification
Responsible for verification and evaluation (i.e. Verification Plan and Verification Results).
Analyses design flaws
Conducts corrective actions (processes PRs & CRs).
3. Quality of work
Is responsible for quality of own design.
Improves designs over time, by applying lessons learned.
Ensures completeness of the (module) documentation.
Is co-responsible for review of own work.
4. Schedule & Efficiency
Defines a reliable schedule for own work in order to support project management.
Reports progress of own activities.
Makes optimally use of known and verified (sub)modules in order to reduce project risks and development effort.
Contributes to balancing amount of work among peer developers.
5. Communication
Communicates with clarity, structure and conciseness both verbally and in writing
6. Coaching
Coaches less experienced colleagues when needed or asked for.

7. Learning & Development (Personal Development)
Maintaining capabilities, increasing added value, enhancing deployment.
Keeps abreast of current technology and deploys new methodologies
Knows technology trends and deploys them
Searches for new challenges to broaden or deepen expertise
Improves areas of weakness (technical, behaviors, attitudes)

Requirement：

BSEE/MSEE
5 years experience in digital design
- Experienced with mixed signal IC design;
- Able to build Verilog-AMS models;
- Able to run mixed-level simulations;
- Experienced with Synopsys & Cadence tool suite;
- A team-worker with a pro-active attitude; Open in communication

POSITION:  DIGITAL LAYOUT ENGINEER-PR （芯片设计工程师-数字后端设计）工作地：上海  
JOB description：
The Digital Layout Engineer (DLE) plays an essential role in the physical implementation of the top-level functional netlist, resulting in an optimally placed, routed and verified chip layout. He/she also supports and advises the development team and third parties (subcontractors, customers) with respect to the physical development of Analog & Mixed Signal modules used in the IC’s.

The DLE has sufficient broad knowledge to co-operate with all other competencies within the project, and establishes and contributes to a co-operative and productive interaction in team working situations.

1. Building up, and maintaining knowledge of:
Schematic, symbol, layout and abstract design, physical topologies and design methodologies.
Translating IC specifications to an optimal placement of PMU modules and I/O pads, in close co-operation with the system/IC architect and the customer.
Creating an optimal routing of critical and non-critical signals, supply trunks and clock trees for the complete top-level IC from a functional netlist.
ESD, EMC, supply strategy, clocking strategy, design for test, and related

2. Layout Verification before Tape Out:
Verifying and completing the IC with DRC/LVS checks, chip-finishing and bonding.
Participating in physical design reviews, also in other projects.
Delivering back-annotated data needed for timing verification of modules, both standalone and embedded in top level circuitry.
Properly tagging of IC layout data bases

3. Communication:
Maintain a network of contacts on physical IC design
Contribute to co-operative and productive team atmosphere
Communicate with conciseness in both one to one and group situations.

Requirement：
BSc-E or MSc-E.
Being knowledgeable on:
(1) Data exchange formats: LEF, DEF, TLF, (R)SPF, SDF and GDS2.
(2) Synopsys IC compiler
(3) Experience in following tools: Place & Route Tools, Skill, Pearl and other script languages, etc.
A pro-active attitude.
Fluent in English

Analog Design Engineer for Smartphone & Tablet Solutions（芯片设计工程师-模拟设计工程师）    工作地：上海  



Department Analog Mixed Signal for Smartphone & Tablet Solution
The BU (Business Unit) Analog Mixed Signal within 3GP develops, produces and sells advanced, highly integrated CMOS system Portable Power Solutions for smartphone & tablet solution. Our main customers are LGE, Nokia, Samsung Sharp and Sony Ericsson. The BU has it’s headquarter in Grenoble and it’s design operations in Grenoble, Catania, Prague and Shanghai. Currently it employs about 300 persons.

Job Description

As an Analog Design Engineer you are a member of our PMU design team. You will be developing analog IP and analog blocks for power management IC. You play an important role in the mixed signal integrated circuits design. The role will cover the full IC design cycle from specification through to testing of engineering samples.

Key Areas of Responsibility
1. Carry out development activities from design, verification to physical validation for mixed signal integrated circuits (Analog, power and digital blocks) for power management IC;
2. Interface with layout team, performing or providing guidance for layout design and controlling layout design and work quality;
3. Evaluate the product with application team to meet customer specification;
4. Debug product to fix incorrect operation and meet customer specification;
5. Work with a project leader to identify tasks and track progress to plan;
6. Work with an architect to define block specification, simulation, verification and physical validation plan;
7. Work with other team members to build up design knowledge and improve way of working;
8. Develop his/her leadership on his/her domain of skills and actions.

Requirements

1. MSEE whose major is analog design;
2. Familiar with CAD tools and environments, i.e., design workstations and UNIX; Familiar with Cadence Spectre, Virtuoso Layout XL;
3. Experience in analog layout design and physical validation;
4. Good command of English;
5. Good team-worker with a pro-active attitude;
6. Experience in PCB design, instrument and measurement, lab skills, and lab evaluation is a plus.


另该客户北京也有大量的物理层软硬件职位，篇幅限制，仅贴出职位title,有兴趣的朋友可以直接联系我，我会将具体信息分享给大家

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如需进一步了解，请将简历发至我的邮箱或通过MSN联系，具体如下：

James Yao

Mail：jamesyao@careerrpo.com

MSN: jamesyao007@hotmail.com