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发表于 2014-9-24 21:38:51
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// VerilogA for Vxa_tb, SARADC_va, veriloga
`include "constants.vams"
`include "disciplines.vams"
`define N 10
module SARADC_va(Vip,Vin,CLK,D);
input Vip,Vin,CLK;
electrical Vip,Vin,CLK;
output [`N-1:0] D;
electrical [`N-1:0] D;
parameter real vmax=1;
parameter real vmin=0;
parameter real one=1.0;
parameter real zero=0.0;
parameter real vth=0.5;
parameter real slack=10.0p from (0:inf);
parameter real trise=4.0n from (0:inf);
parameter real tfall=4.0n from (0:inf);
parameter real tconv=1.0u from (0:inf);
parameter integer traceflag=0;
real sample,vref,lsb,voffset,vdac;
real vd[0:`N-1];
integer ii;
analog begin
@(initial_step or initial_step("dc","ac","tran","xf")) begin
vref=(vmax-vmin)/2.0;
vdac=vref;
lsb=(vmax-vmin);
voffset=vmin;
end
//SAR ADC的行为描述
@(cross (V(CLK)-vth,1,slack,CLK.potential.abstol)) begin
vref=(vmax-vmin)/2.0;
vdac=0;
sample=V(Vip,Vin);
for(ii=`N-1; ii>=0; ii=ii-1) begin
vd[ii]=0;
vdac=vdac+vref;
if(sample>vdac) begin
vd[ii]=one;
end
else begin
vd[ii]=zero;
vdac=vdac-vref;
end
vref=vref/2.0;
end
end
generate i (`N-1,0) begin
V(D[i])<+transition(vd[i],tconv,trise,tfall);
end
end
endmodule
`undef N |
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