社会招聘[Marvell] IC 设计相关职位

wangyl321

Job Title   :   VerificationEngineer(Marvell)

Justification: Support verification for newdesigns in MMP2, such

as ebook controller, ISP verification.

Job Description:

- Build test environment and develop testcases.

- Run power simulation.

- Run gate level simulation.

Qualification:

- Familiar with verilog and C.

- Familiar with system verilog, synthesisare plus.

- Knowledge of perl is a plus.

BS or MS are required

- 2-3 years experience are plus.

Job Title  :   ASIC DesignEngineer (Senior) (Marvell)

Job Duties:

- Perform DFT design and verification oncomplex mixed signal SOC chips. Tasks mainly include MemBist, JTAG, Scan,AC-scan, test compress, ATPG, pattern generation and simulation and silicondebugging.

- Apply low power design concepts,including multiple power domain, power gating, clock gating, and dataretention, to ASIC designs. Develop test benches and test cases and runsimulations.

- Conduct floor planning, placement andtiming closure using Synopsys ICC or Cadence SOC Encounter. Perform static timinganalysis using Primetime. Perform formal verification between RTL and gatelevel netlist using LEC. Participate in real silicon bringing up on ATE.

- Familiar with interfaces such as DDR,USB, PCIE, Ethernet, HDMI etc.

Job Requirements:

The position requires a Bachelor's degreein Electrical Engineering, Computer Engineering, or a related technical fieldand five+ years of progressive, post-baccalaureate experience. Master's degreein stated field with two+ years of experience will also be acceptable.

Must have hands on experience onVerilog_XL, VCS, Synopsys DC, DFT Compiler, PT, Mentor DFT advisor,Mbistarchitect, Fastscan, TestKompress

Job Title   :   Senior DesignVerification Engineer (Senior) (Marvell)

Justification:

To work on next generation of ultra lowpower highly integrated mobile application processor. Candidate will play a keyrole in complex SOC design and verification and system validation.

Candidate will work on many newdevelopments for mobile platform, as well as continue enhancements on existingIPs, and complex SOC integrations, verification and system validations.

Qualification:

- Work experience: BS + 3yr / MS + 1

- Be capable of micro architecturedefinition, module verification planning, performance analysis, RTLimplementation and verification.

- Be familiar with low power designconcepts, like multiple power domain, power gating, clock gating, and dataretention.

- Have system knowledge in mobilecommunication system or multimedia application system.

- Experience on ARM based SOC, DDR, AXI,USB, and MIPI are helpful.

- Used design tools like Verilog_XL, VCS,Synopsys, Spyglass, LEC, etc.

Job Title   :   DFT manager   (Marvell)

Qualifications:

1. BS (MS preferred) in microelectronics,electrical engineering or equivalent with 5+ years of DFT design experience,preferably with large SoC chips.

2. Handy experience on scan, mbist,boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools andRTL/gate simulation.

3. Good communication skill in amulti-national multi-team working environment. Experience with ATE tester andProduction Engineer is a strong plus.

4. RTL design and STA experience is astrong plus.

6. Fluent in both written and spokenEnglish

Description:

DFT team manager

Focus on leading the DFT team for DFTdesign & debugging of leading-edge large SoC, and work with ProductionEngineering team on large volume production.

Job Title   :    Senior /StaffDFT engineer(Marvell)

Qualifications:

1. BS (MS preferred) in microelectronics,electrical engineering or equivalent with 3+ years of DFT design experience,preferably with large SoC chips.

2. Handy experience on scan, mbist,boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools andRTL/gate simulation.

3. RTL design and STA experience is astrong plus.

4. ATE tester experience is a plus.

5. Must be able to communicate in bothwritten and spoken English

6. Good team work spirit and communicationskill.

Description:

Sr. / Staff ASIC DFT design engineer

Focus on DFT design & debugging ofleading-edge large SoC.

Job Title:  (Senior/Staff )Synthesis/Timing Engineer(Marvell)

Candidate will be part of the front endteam for the next-generation Marvell application processor targeted for the PDAand cell phone markets. Responsibilities include logic design, synthesis, andtiming convergence. Interaction with other teams in different geographies willbe a key skill in this position.

Job requirements/Responsibilities include:

·5+ years workexperience in front end ASIC implementation methodology

·Strong understanding ofsynthesis flow using Design Compiler - for a low power (UPF) and high speed-complex SoC

·Hands on experiencewith formal verification tools such as LEC and/or formality

·Must have solidunderstanding of Clock Tree Synthesis using ICC

·Strong STA skills. Musthave thorough knowledge on closing timing at unit and top level

·Ability to build newEDA-methodology-flow using perl, tcl and shell programming would be an addedadvantage

Job Title: (Senior) ICVerification Engineer(Marvell)

Location: Shanghai/Beijing

Candidate will be part of the design teamfor the next-generation Marvell application processor targeted for the PDA andcell phone markets. Responsibilities include pre-silicon verification andpost-silicon bring-up. Interaction with other teams will be a key skill in thisposition.

Qualifications

BS in EE/CS. Preferred candidate will havecompleted Masters degree

Minimum of three years experience.

Additional qualifications include: Good ICverification skills and basic knowledge of logic and circuit design, goodcommunication and problem solving skills.

Candidate should be familiar with low powerdesign techniques.

Candidate must have the ability to work ina diverse team environment, have familiarity with industry standard ASIC designtools and flow, have knowledge of microprocessors and computer systemarchitecture, and experience with professional verification tools such asSystem Verilog, VMM/OVM/UVM or System C/Testbuilder, etc. Good knowledge ofPerl and shell programming would be an added advantage.

Job Title: (Senior) ASICEngineer(Marvell)

ualifications:

1.BS (MS preferred) in microelectronics,electrical engineering or equivalent with 3+ years of ASIC front-end designexperience, preferably with communication chips.

2. Familiarity with SoC design andintegration.

3. Handy experienced with standard designflow and tools on various design phases, including documentation, coding, lint,version control, STA, and RTL/gate simulation.

4. Understanding with 2G and 3G algorithmsand protocol is a plus.

5. Must be able to communicate in bothwritten and spoken English

6. Good team work spirit and communicationskill.

Description:

ASIC design engineer

Focus on ASIC implementation of algorithms,control modules and SoC integration.

Job Title: (Physical ImplementationEngineer(Marvell)

Job Description:

COT-PD is a core technical department ofMarvell. The department is professional on the deep-sub micron technology on28nm, 40nm chips, advanced large scale low power chips, high performance chips,flip-chips ...etc. The department is specialized on physical implementation,physical verification, signoff, tapeout, library and technology development.COT-PD has very good pattern-ship with all BU in Marvell, Storage, StorageEnterprise, PHS, Datacom, Reading Channel, Wireless, AP, Analog ...etc anddelivers about 400 tapeouts very year. Currently COT-PD has over 150 people on7 sites over global, SC, AV, Austin, Chandler, Shanghai, Chengdu, Bangalore.

COT-PD is keeping growing as the designcomplexity increasing, deep sub-micron technology developing. You are welcometo join COT-PD of Marvell if you are crazy on the technology and methodology ofIC and silicon.

Qualification:

- BS/MS in EE/CS required.

- Three or more years of hands-onexperience in IC physical design implementation and TAPEOUT.

- Proven track records of workingindependently on place-and-route project running and design closure with power,timing, SI, Physical... etc

- Experience with Cadence, Magma, Synopsysplace-and-route tool and physical design project implementation Includingfloorplan, power plan, placement, physical synthesis, CTS, routing, SI fixingand timing closure

- Knowledge of physical design rules withMagma, Cadence, Synospsys Format and RC extraction

- Good programming skill. Capable ofwriting Tcl or Perl.

- Familiar with Verilog HDL, SDC, timing,Spice Netlist

- In-depth understanding of how the PnRtools works, Design Constraints, fabrication processing steps used in majorfabrication industries.

- Self-motivated team worker, good verbaland written communication skills in English

- Technical and team leadership proffered.Previous management experience highly desired.

Marvell 2012 社招最新职位，如果有兴趣请发送英文简历到snakkewang@gmail.com，会帮你内部推荐，谢谢。

shuli124

回复 1# wangyl321

shuli124

回复 1# wangyl321
请问都是上海的job么？成都这边有没有做design的职位？

wangyl321

回复 3# shuli124
   抱歉，成都这边只有ASIC后端设计的职位

jinnon

回复 1# wangyl321


    有深圳的职位没？

wangyl321

回复 5# jinnon

抱歉，深圳也没有IC相关职位，主要是上海浦东个这边，谢谢关注

forever5714

请问有北京的职位吗？

wangyl321

应楼上，更新北京职位：

Title: ASIC Design Engineer

Department:Cellular Engineering

Location:Beijing

Qualifications:

- BS (MSpreferred) in microelectronics, electrical engineering or equivalent with 3+years of ASIC front-end design experience, preferably with communication chips.

- Familiaritywith SoC design and integration.

- Handyexperienced with standard design flow and tools on various design phases,including documentation, coding, lint, version control, STA, and RTL/gatesimulation.

- Understandingwith 2G and 3G algorithms and protocol is a plus

- Must be ableto communicate in both written and spoken English

- Good teamwork spirit and communication skill.

Description:

ASIC designengineer

Focus on ASIC implementation of algorithms, control modules and SoCintegration.

Title :
(Senior)ASICEngineer

ExternalDescription

Candidate willbe part of the design team for the next-generation Marvell applicationprocessor

targeted for the PDA and cell phone markets. Responsibilities include logicdesign, verification,

synthesis, and timing convergence. Interaction with other teams will be a keyskill in this

position.
Qualifications

BS in EE/CS.Preferred candidate will have completed one year of Masters program.

Minimum ofthree years experience.

Additionalqualifications include: Good logic and circuit design knowledge along withknowledge of basic verification techniques, good communication and problemsolving skills.

Candidate should have experience in low power design techniques.

Candidate musthave the ability to work in a diverse team environment, have familiarity withindustry standard ASIC design tools and flow, have knowledge of microprocessorsand computer system architecture, and experience with Verilog and/or VHDL. Goodknowledge of Perl and shell programming would an added advantage

Title :
(Senior) IC VerificationEngineer

Location:Shanghai/Beijing

Candidate willbe part of the design team for the next-generation Marvell applicationprocessor targeted for the PDA and cell phone markets. Responsibilities includepre-silicon verification and post-silicon bring-up. Interaction with otherteams will be a key skill in this position.
Qualifications
BS in EE/CS. Preferred candidate will have completed Masters degree
Minimum of three years experience.
Additional qualifications include: Good IC verification skills and basicknowledge of logic and circuit design, good communication and problem solvingskills.
Candidate should be familiar with low power design techniques.
Candidate must have the ability to work in a diverse team environment, havefamiliarity with industry standard ASIC design tools and flow, have knowledgeof microprocessors and computer system architecture, and experience withprofessional verification tools such as System Verilog, VMM/OVM/UVM or SystemC/Testbuilder, etc. Good knowledge of Perl and shell programming would be anadded advantage.

Title :
(Senior/Staff ) Synthesis/Timing Engineer

Candidatewill be part of the front end team for the next-generation Marvell applicationprocessor targeted for the PDA and cell phone markets. Responsibilities includelogic design, synthesis, and timing convergence. Interaction with other teamsin different geographies will be a key skill in this position.
Job requirements/Responsibilities include:
·5+ years work experience in front end ASICimplementation methodology
·Strong understanding of synthesis flow usingDesign Compiler - for a low power (UPF) and high speed- complex SoC
·Hands on experience with formal verificationtools such as LEC and/or formality
·Must have solid understanding of Clock TreeSynthesis using ICC
·Strong STA skills. Must have thorough knowledgeon closing timing at unit and top level
·Ability to build new EDA-methodology-flow usingperl, tcl and shell programming would be an added advantage

wangyl321

顶一下~~~

shijunhn

上海有CAD engineer职位吗？我是做CAD的，有意请联系我的邮箱shijunhn@hotmail.com