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本帖最后由 vivikinghjf 于 2012-1-17 15:08 编辑
谱瑞集成电路（上海）有限公司
职位： Digital Verification Engineer
RESPONSIBILITIES: - Develop and execute verification plan - Develop and maintain verification environment from unit level to system level - Define and implement functional/code coverage plan - Code/functional coverage analysis - Responsible for running both RTL & gate level simulation - Develop testing and regression methodologies for new verification flow - Develop/maintain/enhance environment tools/scripts/makefiles
REQUIREMENTS: - Proficient and experienced with the C/C++ program - Experience in ASIC design or verification - Proficient with Verilog HDL - Proficient with one or more scripting languages, such as Shell, Perl and TCL - Familiar with logic simulators and debug tools (VCS, NC-Verilog, Verdi etc) - Familiar with hardware verification language(Vera, Specman-E, SystemC, SystemVerilog), SystemVerilog is a strong plus - Skill on Makefile is required - Experience with Verilog PLI is a plus - Master degree in Electrical Engineering/Computer 说明：公司介绍请看2011中国IC设计十佳No.1:http://laoyaoba.com/wordpress/?p=4209 职位要求：职位要求并没有硬性的规定。软件编程佳且具备一定硬件基础的人都可以考虑，计算机系或学嵌入式的比较合适。 有兴趣的同学朋友们欢迎请将简历发到viking.huang@paradetech.com | 
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发表于 2012-1-17 15:07:20
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