IEEE--Design Considerations for LowPower HighSpeed CMOS AD Converters

semico_ljj

IEEE--Design Considerations for LowPower HighSpeed CMOS AD Converters
by
Thomas B. Cho, David W. Cline, and Cormac S.G. Conroy*, and Paul R. Gray
Department of Electrical Engineering and Computer Sciences,
University of California, Berkeley

Abstract

This paper reviews architectural and circuit design considerations
for realization of low power dissipation in high-speed
CMOS A/D converters. Basic limitations on achievable
power dissipation in MOS samplers and quantizers is first discussed.
Then a number of practical design aspects are illustrated
with discussion of a 10-bit, 20-Msample/s pipeline A/D
converter[1] implemented in 1.2-µm CMOS technology
which achieves a power dissipation of 35 mW at full speed
operation on a 3.3V power supply.

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