上海高通Atheros招聘Analog circuit deigner, RF, SW driver engineer若干

crow016

上海高通Atheros招聘Analog layout designer,Analog circuit deigner, RF engineer, SW driver engineer若干, 公司最后一次内部推荐机会，各位走过路过不要错过。部分JD如下, 简历发至 abenhuang016@126.com, 多谢合作。

  Analog layout designer

DESCRIPTION OF FUNCTION & RESPONSIBILITY: 1: Layout block and top-level analog circuit layout. 2: Build analog and digital pad library. 3: Extract special layout for post simulation for circuit designer.

EDUCATION: Bachelor degree in Semiconductor, Electronics Engineering, More than three years of analog layout experience.

EXPERIENCE: 1: Familiar with Virtuoso, layout XL, Composer, Calibre physical verification. 2: Solid fundamental knowledge in layout, such as matching, floor plan, size estimation. 3: Able to work independently in all aspects of IC layout design, including floor planning, cell, block and top-level layout, and verification. 4: Experience in analog layout: Bandgap, PLL, LDO, ADC, DAC etc. 5: It will be helpful to be familiar with PERL and CAD. And RF layout experience is preferred.

Analog circuit deigner

DESCRIPTION OF FUNCTION & RESPONSIBILITY:

1) Design analog, mixed-signal circuits for an integrated CMOS transceiver. Circuits may include amplifiers, comparators, filters, ADC/DAC, PLL, switched-capacitor circuits, SERDES, etc.
2) Work closely with layout designers.
3) Work with system integration team to define specifications.
4) Test prototypes and help develop production test methodology.

EDUCATION:
MS or above in Electrical / Electronic Engineering.

EXPERIENCE:
Master with 6+ years or PhD with 2+ years’ experience with emphasis in analog, mixed-signal, integrated circuit design.

Familiar with circuit design, simulation, physical layout and the use of various design CAD tools such as Spectre, SPICE, etc.

Familiar with usage of Lab equipment such as logic analyzer, oscilloscope, signal generator, power supplies etc.