analog/layout design上海张江美资上市公司内部推荐

hbchens

张江美资上市公司(NASDAQ)，待遇优厚，内部推荐，有意向的发mail给我:chens154@163.com
以下职位最好是硕士两年，本科四年以上工作经验，当然优秀的应届及较少工作经验的人也可以。

职位描述1:Analog IC Design Engineer(模拟集成电路设计工程师)
Responsible for the design development and characterization of embedded analog circuits,such as high speed
transceiver (receiver and transmitter), SerDes, DLL, CDR, PLL. Design experience of mixed-signal and RTL coding is a
significant plus. Needs to work closely with digital,system and test engineers to develop high speed blocks in image
sensor and bridge chip products
负责内嵌的模拟电路的定义与设计研发，比如高速收发器（接收器和发送器），串行解串器，延迟锁定环，时钟数据恢复，锁相环等
。
如具备混合信号设计和RTL编码能力更好，（他/她）将会需要和数字、系统和测试工程师紧密合作来研发用于图像传感器和桥接芯片
的高速电路模块。
OR Responsible for the design development and characterization of embedded analog circuits, such as high speed I/O,
SerDes etc. Design and debug experience on high speed (multi GHz) signal integrity (SI), package and PCB boards is a
significant plus. Need to work closely with system and test engineers to develop high speed I/O, package/board, and
system clocks in image sensor and bridge chip products.
负责内嵌的模拟电路的定义与设计研发，比如高速I/O电路，串行解串器等。如拥有高速电路（multi GHz）信号完整性(SI)，封装和
PCB板等经验更好，（他/她）将会需要和系统以及测试工程师紧密合作来研发用于图像传感器和桥接芯片的高速I/O电路、封装/板和
系统时钟电路。
70% job responsibilities
- Analog design, simulation and verifications .
- RTL behavior modeling and NC verilog simulations.
- IP and design spec documentations
- layout design and support. He/she need to get involved into layout and optimize the layout for high speed or high
precision performance directly.
- Chip debug and support.
70%工作职责
- 模拟设计，仿真和验证
- RTL行为级建模和NCverilog仿真
- 创建IP和设计说明的文档
- 版图设计和支持，他/她需要直接介入版图工作并优化版图以提升高速或者高精度电路的性能。
30% job responsibilities
- Advance designs and test chips in R & D development.
- Top level signal integrity and power integrity check
- Interface verifications between analog and digital
30%工作职责
- 研发类芯片中的先进电路设计和测试
- 顶层电路的信号完整性和电源完整性检验
- 模拟/数字接口验证
Recruitment requirement (Degree, experience, etc.).
- Master in EE,
- 2+ years analog design experience is preferred.
- Familiar with Cadence analog design flow and Spice/SpectreMDL simulations.
- Past design experience in high speed analog/mixed-signal blocks: PLL, DLL, Tx/Rx, CDR, etc.
- Familiar with device mismatch, signal noise, phase noise, jitter and jitter tolerance.
- Verilog & verilogA coding and simulation is a significant plus.
- Familiar with USB, MIPI, HDMI and other high speed standard is preferred
- Shell/Perl script skills.
- Strong trouble shooting skills, good written and communication skills
Also, the position can be a senior design engineer level if he or she has 5+ design experience.
招聘要求（学历，经验等）

hbchens

职位描述2:Analog IC Design Engineer(模拟集成电路设计工程师)

Position Overview:
Block level specification definition, circuit design, simulation, test and debug for analog baseband blocks in RF

transceiver such as ADC and DAC



Primary (70%):
1.Performs block level specification definition, schematic design &simulation
2.Critical block layout design, post-layout simulation
3.test and debug in lab
4.Write design report,test plan and test report of RF block

Secondary (30%):
Supervising layout engineer in some auxiliary block layout design

Requirements:
Experience/Skills:
1.Bachelor's or Master's degree in Microelectronics or equivalent areas,
2.Minimum 2 years experience in mixed signal circuit design for Master's degree,Minimum 4 years experience for

Bachelor's degree
3.Advanced knowledge of CMOS analog circuit design in one or more of the following areas with deep sub-micron

process(0.13um, 90nm or 65nm):pipeline ADC,DAC,LDO,VGA,Filter,reference etc.
4.For ADC design, successful experience of pipeline ADC with spec more than "9bit 40MHz" is mandatory.
5.Proficiency in layout design, verification (DRC, LVS)
6.Advanced skills in Cadence tools (Virtuoso, ADE, etc.) and circuit simulation tools (Spice, Spectre, SpectreRF,

Ultrasim, etc.)

职位描述3:Analog IC Design Engineer(模拟集成电路设计工程师)

Position Overview:
Specification definition, circuit design, simulation, test and debug for Audio Codec



Primary (70%):
1.Performs whole chip and block level specification definition, schematic design &simulation
2.Critical block layout design, post-layout simulation
3.test and debug in lab
4.Write design report,test plan and test report

Secondary (30%):
Supervising layout engineer in some auxiliary block layout design

Requirements:
Experience/Skills:
1.Master's degree in Microelectronics or equivalent areas,
2.Minimum 2 years experience in audio codec project.
3.Advanced knowledge of one or more critical blocks in audio codec: Audio sigma delta ADC, Audio sigmal delta DAC,

Audio Power Amplifier, etc.
4.Proficiency in layout design, verification (DRC, LVS)
5.Advanced skills in Cadence tools (Virtuoso, ADE, etc.) , circuit simulation tools (Spice, Spectre, SpectreRF,

Ultrasim, etc.) , matlab

职位描述:Sr. Backend Engineer 资深后端工程师

Description:

1. Responsible for IC implementation from netlist to GDSII including floorplaning,Place and route, power analysis,

crosstalk analysis, timing closure and physical verification.

2. Help develop/improve backend design flow/methodology.

Requirements:
1. BS or MS degree in EE or CS related, and more than 3 year backend design experience.
2. Successful tapeout experience is a must.
3. Familiar with physical design flow/tools. Experience with Cadence SOC-Encounter is a plus.
4. Analog/Mixed-signals design experience is a plus.
5. Good programming skill (perl/TCL) is a plus.
6. Must be a good team player and have a good communication skills

evistera

HEN HAO HEN HAO , JIU SHI JIN BU LIAO,

pillar_chen

is the company Marvell?

edwardk

学习中。。。。。。。。。。。。

edwardk

学习中。。。。

inter0211

积分不够了，顶个贴