西安华芯半导体有限公司

jessie1

设计验证工程师Design and Functional Verification Engineer (DFV)
职位描述：
Responsibilities:
1. Be responsible for the verification plan according the design-specification.  
2. Work as an independent designer to check the design functionality  to cover all the design requirements at module level  sub-system level.  
3. Test-bench  Test-case generation, simulation  debug to verify the design according to design specification  verification plan.
4. Test pattern generation  support the debug during chip test.
5. Work as interface with Front-End (Concept engineer) to optimize or review the design architecture.
6. Work as interface with Back-End (APR  STA Engineer) to optimize or review the design implementation (timing constrain, floor-plan, clock tree generation  so on).
7. Verilog or VHDL coding according to design specification or external/internal IP integration.
8. Support the post simulation with gate-level verilog or VHDL netlist.  

Requirements:
1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field， 2+ Years of related working experience.  
2. Experience with RTL coding  simulators (anyone of Modelsim, NC-sim, Specman).
3. Basic knowledge of script language (Perl, TCL, C-language  so on)  
4. Basic knowledge of logic synthesis (Design Compiler), APR(IC-Compiler), Static Timing analysis (Prime-Time)  DFT.
5. Knowledge about 2G  3G hset baseb Architecture, ARM, AMBA Architecture is a big plus.  
6. Team oriented, love to work in young, international  highly motivated teams.
7. Good comm of English  

jobic_cn@126.com

混合电路设计工程师(存储器IP)Mixed-signal Design Engineer(memory IP)
职位描述：
Responsibilities:  
1. Responsible for  high-performance  memory  IP design, verification, integration  test.
2. CMOS circuit design for highly integrated memory devices, Memory Core, Sense Amplifier, Address decoder (Flash/SRAM/DRAM).
3. Check layout  physical implementation.
4. Circuit optimization  verification by simulations using HSPICE , Nanosim, NC-Sim or other equivalent tools.
5. Support other teams in the IP test  qualification.  
6. Support users in the IP integration  verification.  
  
Requirements:  
1.  Either Bachelor, Master in Microelectronics, Electronic Engineering, with equivalent experience.
2.  Strong experience with developing memory IP, especially SRAM IP.
3.  Expertise with CAD tools such as Schematic entry, HSPICE, Nanosim, etc.
4.  Experience in layout design  verification (DRC/LVS)  
5.  Knowledge in SoC design methodology  semiconductor process.
6.  High level of self-motivation  ability to be a good team player.  
7.  English language skill in writing  speaking is a must.

IC人才网原链：http://www.jobic.cn/Html/JobDetails/12817.html
10月份注册简历赢ipad:http://www.jobic.cn/Resume/Register.aspx
邮箱：jobic_cn@126.com
电话：0755-26490606

jessie1

工作地点在西安啊～～～

jessie1

是啊～～～希望大家多多给力

jessie1

呵呵～～～～

fhffhf

很好的工作！

jessie1

支持一下～～～

helenhappy

哈哈，好像是一家不错的公司。就是要求有点高啊～～～

helenhappy

给力～～～～～～～～～

89757

工作环境，待遇如何啊？