硕士论文 On-Chip Low Jitter Clock Generation

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On-Chip Low Jitter Clock Generation
硕士论文
TABLE OF CONTENTS

CHAPTER 1. INTRODUCTION 1
1.1 Motivation 1
1.2 Organization 3

CHAPTER 2. FUNDAMENTALS OF PLLS 5
2.1 Definition of PLLs 5
2.2 Components of PLLs 6
2.2.1 Voltage-Controlled Oscillator (VCO) 7
2.2.2 Phase Detector or Phase Frequency Detector 9
2.2.3 Charge-pump and Loop filter 12
2.3 Applications of PLLs 13
2.3.1 High-Speed Serial Link 13
2.3.2 Fractional-N Synthesizer 14
2.4 Delay-Locked Loops 15

CHAPTER 3. THEORY AND JITTER ANALYSIS OF PLLS 16
3.1 Loop Characteristics 16
3.1.1 Second Order Systems 16
3.1.2 S-domain Model of PLLs 21
3.2 Definitions of Jitter 25
3.3 Jitter in Ring Oscillators 26
3.4 Noise Sources of PLL 28
3.5 Jitter Optimization of PLL 31
3.5.1 PLL Noise Transfer Function 31
3.5.2 Jitter due to VCO Noise 33
3.5.3 Jitter due to Input Clock Noise 35

CHAPTER 4. DESIGN AND SIMULATION OF A LOW-JITTER PLL 38
4.1 Design Consideration 38
4.2 Design of VCO 40
4.2.1 A VCO with Simple Noise Canceling Technique 41
4.2.2 A self-biased VCO 43
4.3 Design of Charge-Pump and Loop Filter 49
4.4 Design of PFD and Frequency Divider 51
4.5 Simulation and Discussion 53
4.6 Proposed VCO Architecture 59

CHAPTER 5. CONCLUSIONS AND FUTURE WORK 64
REFERENCE 66

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