dft菜鸟求助：有关dftadvisor插扫描连的问题

shaoqingtju

DFT菜鸟求助：我在进行扫描连插入时，选用full_scan,为什么run以后都是nonscan的，显示的scannable的数目是0。刚接触dft，求牛人解答，强烈感谢。。。。。。

shaoqingtju

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bingling512

drc检查没有问题吗？

shaoqingtju

回复 3# bingling512


    drc检查报了两个Warning，麻烦看看我的log。用的是libcomp转的.v的库。
Compiling library  ...
//  Reading DFT Library file lib.atpg
//  Finished reading file lib.atpg
//  Reading Verilog Netlist ...
//  Reading Verilog file tcore_7ns.v
//  Finished reading file tcore_7ns.v
//  Warning: 591 cases: Unused net in DFT library model
//  Warning: 15 cases: Undriven net in netlist module
//  Note: Invoke with '-load_warnings' to see detailed library and netlist load warnings
//  command: add black box -auto
//  command: analyze control signals -auto_fix
//  Warning: Rule FN1 violation occurs 15 times
//  Flattening process completed,  design_cells=23282  library_primitives=49881  netlist_primitive=105  sim_gates=52623  PIs=192  POs=186  CPU time=0.31 sec.
//  ---------------------------------------------------------------------------
//  Begin circuit learning analyses.
//  ---------------------------------------------------------------------------
//  Equivalent gates=443   classes=199   CPU time=0.13 sec.
//  Learned gate functions: #BUFs=2 #XORs=327 #MUXs=314
//  Learning activity limit exceeded: static learning process was truncated.
//  Learning completed, implications=19906, tied_gates=241, CPU time=0.11 sec.
//  ---------------------------------------------------------------------------
//  Begin control signals identification analysis.
//  ---------------------------------------------------------------------------
//  Identified 1 clock control primary inputs.
//     /clk (1) with off-state = 0.
//  Identified 1 set control primary inputs.
//     /reset_b (2) with off-state = 1.
//  Identified 1 reset control primary inputs.
//     /reset_b (2) with off-state = 1.
//  Identified 0 read control primary inputs.
//  Identified 0 write control primary inputs.
//  ---------------------------------------------------------------------------
//  Total number of internal lines is 6222 (2074 clocks, 2074 sets , 2074 resets, 0 reads, 0 writes).
//  Total number of controlled internal lines is 4148 (2074 clocks, 9 sets , 2065 resets, 0 reads, 0 writes).
//  Total number of uncontrolled internal lines is 2074 (0 clocks, 2065 sets , 9 resets, 0 reads, 0 writes).
//  Total number of added primary input controls 2 (1 clocks, 0 sets , 1 resets, 0 reads, 0 writes).
//  ---------------------------------------------------------------------------
//  command: set scan type mux_scan
//  command: setup scan identification full_scan
//  command: setup scan insertion -sen scan_en
//  Warning: Pin 'scan_en' does not exist and will be created when inserting test logic
//  command: setup scan insertion -ten test_en
//  Warning: Pin 'test_en' does not exist and will be created when inserting test logic
//  command: set test logic -clock on -reset on -set on
//  command: add scan pins chain1 scan_in1 scan_out1
//  Warning: Scan-in 'scan_in1' does not exist and will be created when inserting test logic
//  Warning: Scan-out 'scan_out1' does not exist and will be created when inserting test logic
//  command: add scan pins chain2 scan_in2 scan_out2
//  Warning: Scan-in 'scan_in2' does not exist and will be created when inserting test logic
//  Warning: Scan-out 'scan_out2' does not exist and will be created when inserting test logic
//  command: add scan pins chain3 scan_in3 scan_out3
//  Warning: Scan-in 'scan_in3' does not exist and will be created when inserting test logic
//  Warning: Scan-out 'scan_out3' does not exist and will be created when inserting test logic
//  command: add scan pins chain4 scan_in4 scan_out4
//  Warning: Scan-in 'scan_in4' does not exist and will be created when inserting test logic
//  Warning: Scan-out 'scan_out4' does not exist and will be created when inserting test logic
//  command: add scan pins chain5 scan_in5 scan_out5
//  Warning: Scan-in 'scan_in5' does not exist and will be created when inserting test logic
//  Warning: Scan-out 'scan_out5' does not exist and will be created when inserting test logic
//  command: add scan pins chain6 scan_in6 scan_out6
//  Warning: Scan-in 'scan_in6' does not exist and will be created when inserting test logic
//  Warning: Scan-out 'scan_out6' does not exist and will be created when inserting test logic
//  command: add scan pins chain7 scan_in7 scan_out7
//  Warning: Scan-in 'scan_in7' does not exist and will be created when inserting test logic
//  Warning: Scan-out 'scan_out7' does not exist and will be created when inserting test logic
//  command: add scan pins chain8 scan_in8 scan_out8
//  Warning: Scan-in 'scan_in8' does not exist and will be created when inserting test logic
//  Warning: Scan-out 'scan_out8' does not exist and will be created when inserting test logic
//  command: set system mode dft
//  ---------------------------------------------------------------------------
//  Begin scan chain identification process, memory elements = 2074.
//  ---------------------------------------------------------------------------
//  ---------------------------------------------------------------------------
//  Begin scannable cell rules checking for 2074 nonscan memory elements.
//  ---------------------------------------------------------------------------
//  2074 non-scan memory elements ignored for scannability checks.
//  0 non-scan memory elements identified as scannable.
//  ---------------------------------------------------------------------------
//  Begin scan clock rules checking.
//  ---------------------------------------------------------------------------
//  2 scan clock/set/reset lines have been identified.
//  All scan clocks successfully passed off-state check.
//  Warning: There were 2 clock rule C2 fails (clock capture ability check).
//  ---------------------------------------------------------------------------
//  Begin gating checking
//  ---------------------------------------------------------------------------
//  ---------------------------------------------------------------------------
//  Checking clock set and reset for 0 non-scannable sequential instances
//  ---------------------------------------------------------------------------
//  0 sequential instances can be gated to be scannable
//  0 sequential instances remain non-scannable
//  ---------------------------------------------------------------------------
//  Checking test clocks
//  ---------------------------------------------------------------------------
//  Number of test clocks required = 0
//  command: run
//  Number of targeted sequential instances = 0
//  Performing scan identification ...
//  Total sequential instances identified = 0
//  command: report drc rules -All_fails > report/tcore_test.drc
//  ... writing to file report/tcore_test.drc
//  command: insert test logic -scan on -edge merge -clock merge -number 8
//  Warning: The "-Edge Merge" option is specified. Lockup latch insertion may
//           be required at the transitions of the edge domains in the same chain
//           for correct operation!
//  Error: Number of chains specified (8) is greater than number of scan cells (0)
//         'DOFile test_tcore,do' aborted at line 24
//  command: exit

bingling512

回复 4# shaoqingtju


你用的什么工具？我可能没用过这个工具，可能很难给出有效建议。

不知道这个工具能不能像DC一样把有violation的寄存器以及是什么类型的violation（是复位不可控还是时钟不可控……）都报出来。
另外，从log看我感觉工具是没有找到能插链的寄存器，你看看是不是相应的信号没有定义完全（比如时钟，复位，模式信号等）。

shaoqingtju

回复 5# bingling512


      使用的是mentor的design for test，刚才看到了论坛上其他筒子也遇到了相同的问题，据他说是atpg lib的问题，不过我用了smic转门给这个软件做的库还是不行，另外不会是信号的问题吧，脚本里有自动分析控制信号的命令。
      不过还是谢谢你给出的建议啊

squall418

我也遇到了同样到问题，哪位高手能来解决下啊，求助，急急！！！

bywater

你的atpg库有问题，多半里面没有scan cell与non_scan cell对应的信息，或者信息有误。另外一个原因有可能是non_scan cell的时钟不可控，这也可能导致这个结果。

fxcprince

我也遇到这个问题了，谁有正确方法吗？

shaoqingtju

额，这个问题我自己解决的，因为使用libcomp进行转换的lib中没有scan definition，必须自己手动添加，里面主要有SI，SO，SE等signal的指定，以及scan cell与non scan cell的对应信息。只能写个脚本添加了