Optimum phase-acquisition technique for charge-pump PLL

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: Analog AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 9, SEPTEMBER 1997 729
Optimum Phase-Acquisition Technique for Charge-Pump PLL
Gyoung-Tae Roh, Yong Hoon Lee, and Beomsup Kim, Senior Member, IEEE

Abstract—In this paper, we propose a new optimum phaseacquisition
algorithm controlling the loop gain of a chargepump
PLL (CP-PLL) in the sense of the MMSE criterion. A
set of recursive difference equations minimizing rms jitter of
output phase is derived to obtain an optimum gear-shifting
sequence with a zero-phase start (ZPS) assumption. It is shown
that the optimum gear-shifting sequence is independent of the
variance of the input phase jitter. A procedure for applying
this sequence to the design of CP-PLL circuits is described.
Both behavioral simulation and HSPICE circuit-level simulation
demonstrate that the proposed design leads to an efficient CPPLL
having both fast acquisition and significant jitter reduction
characteristics. The optimal gear-shifting CP-PLL outperforms
the conventional CP-PLL’s. These methods can be used for clock
recovery applications such as data communication receivers, disk
drive read/write channels, and local area networks, as well as for
other applications requiring very short initial preamble periods.
Index Terms— Charge–pump PLL (CP–PLL), gear-shifting,
MMSE criterion, optimum sequence, phase-acquisition, zerophase
start (ZPS).






PERFORMING TRANSIENT ANALYSIS ON PLL FREQUENCY SYNTHESIZERS

A PLL can be considered a subsystem within a larger communications system, so
it is appropriate to analyze this type of network with the help of a system-level
simulator. The use of flexible behavioral models within the simulator allows only a
few parameters to be entered before simulation can be performed. Model detail
may also be added as it becomes available to the designer, which permits early
prototyping as well as full system characterization.

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entered before simulation can be performed. Model detail
may also be added as it becomes available to the designer, whi

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PERFORMING TRANSIENT ANALYSIS ON PLL FREQUENCY SYNTHESIZERS

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