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PhD with 3+ years of industrial experience or MSEE with 6+ years of industrial experience in ASIC design -
3+ years or more years of experience in physical design of deep submicron digital ASIC chips -
Hands on experience in large scale ASIC chip physical design -
Knowledgeable in all aspects of deep submicron ASIC design flow -
Successfully gone through several complete product development cycles -
Demonstrate leadership and work well with cross-functional teams -
Good listening, writing and speaking English -
Good communication skills, strong interpersonal skills and the flexibility -
Dedicated, hard working and good team player -
Familiar with Back-End (physical design) EDA tools -
Familiar with Front-End EDA tools is a plus -
Familiar with Unix/Linux environment and good at scripts
有意者请将简历发送到:polo.zhang@amd.com |