谁能帮忙分析一下OpenVera和Systemverilog的区别和优劣势啊

meijingguoyu · 发表于 2011-6-10 20:59:42

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本帖最后由 meijingguoyu 于 2011-6-10 21:02 编辑

OpenVera和Systemverilog同为synopsys公司的验证语言，请问SV相比vera的具体优势在哪里啊，能详细介绍下吗？
这是别人在网上做的验证语言使用率的调查，欢迎参考，大家也可以说说其他验证语言的优势和发展，谢谢
Verification Methodology Poll Results

« Quick Update On Verification Methodology Poll
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Verification Methodology Poll Results
Last week I initiated a poll of verification methodologies being used for functional verification of ASICs. Unlike other polls or surveys, this one was done in a very “open” fashion using a website that allows everyone to view the raw data. In this way, anyone can analyze the data and draw the conclusions that make sense to them, and those conclusions can be challenged and debated based on the data.
What happened next was interesting. Within 48 hours, the poll had received almost 200 responses from all over the world. It had garnered the attention of the big EDA vendors who solicited their supporters to vote. And, as a result, had became a focal point for shenanigans from over-zealous VMM and OVM fans. I had several long nights digging through the data and now I am ready to present the results.
As promised, here is the raw data in PDF format and as an Excel workbook. The only change I have made is to remove the names of the individual 249 respondents.
In summary, the results are as follows:

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(Note: The total is more than the 249 respondents because one respondent could be using more than one methodology.)
Regarding the big 3 vendors, the data shows a remarkable consistency with Gary Smith’s market share data. There are 85 respondents planning to use the Synopsys methodologies (VMM,RVM, or Vera) and there are 150 respondents planning to use the Mentor or Cadence methodologies (OVM, AVM, eRM, e). That represents 36% for Synopsys and 64% for Mentor/Cadence. Gary’s data shows Synopsys with 34% market share, Mentor with 35%, and Cadence with 30%.

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I’ll share some more insights in upcoming posts. In the meantime, please feel free to offer any insights that you have through your comments. Remember, you too have access to the raw data. This invitation includes the EDA vendors. And feel free to challenge my conclusions … but back it up with data!
harry the ASIC guy

TommyGG · 发表于 2011-6-18 12:13:12

（1）OpenVera是专门用于Verification的语言，SV是Design+Verification的语言。
（2）对于验证来说，二者差不多。
（3）OpenVera的语法更接近于C++，SV的语法更接近于Verilog，熟悉Verilog的工程师对SV更容易上手。
（4）方法学上，OpenVera只有RVM，SV有VMM、OVM、UVM等。
（5）SVA比OVA好用。
（6）最重要的是，OpenVera+RVM，Synopsis早已停止维护了，其退出历史舞台是早晚的事。