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本帖最后由 cjsb37 于 2013-4-29 09:00 编辑
小弟刚开始学用AccelDSP工具跑DSP设计的流程,做的实验在跑到综合后,轮到实现Implement步骤时报错,错误如下:
Running delay-based LUT packing...
#ERRORack:1653 - At least one timing constraint is impossible to meet because
# component delays alone exceed the constraint. A timing constraint summary
# below shows the failing constraints (preceded with an Asterisk (*)). Please
# use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and
# PCF files to identify which constraints and paths are failing because of the
# component delays alone. If the failing path(s) is mapped to Xilinx components
# as expected, consider relaxing the constraint. If it is not mapped to
# components as expected, re-evaluate your HDL and how synthesis is optimizing
# the path. To allow the tools to bypass this error, set the environment
# variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
#
#
# For more information about the Timing Analyzer, consult the Xilinx Timing
# Analyzer Reference manual; for more information on TRCE, consult the Xilinx
# Development System Reference Guide "TRACE" chapter.
#
它说是时序有一处错误,需要用Timing Analyzer分析,但是我找不到这个工具,请问遇到这种问题应该如何定位错误源,怎么分析!!!
另外,我看的是Xilinx ISE Design Suite 10.X FPGA开发指南 DSP 、嵌入式与高速传输篇这本教材,上面讲到用AccelDSP跑流程给我的感觉是在工具界面按它给的流程点按钮,从验证浮点程序到Implement,最后还有验证门级网表,请问这些跑完如何才能产生下载到Xilinx开发板上的bitstream!!!
非常感谢
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