Sr.Digital Verification Engineer/atheros

liu_uestc · 发表于 2011-3-7 18:11:29

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

×

Job Title:Sr.Digital Verification Engineer
Req Number: 2011107
QUALIFICATION (DETAIL):
Education:
BS/MS degree in Electrical Engineering, Computer Science, or related field
Experience:
Minimum of 7 years ASIC Verification experience in a product development environment
-Proven verification and superior debugging skills in large ASIC designs
-Rich experience with Specman E or System Verilog or Vera or OpenVera
-Rich ASIC design skills is highly desirable
-Knowledge of data and telecommunication networking(IP/Ethernet) is a plus
-Experience with one or more scripting languages(TCL/Perl/Python) is desired
-Strong written and verbal communication skills
-Adaptable to evolving customer requirement
DESCRIPTION OF FUNCTION & RESPONSIBILITY:
-Lead a design verification team to fully verify ASIC product chip
-Develop reusable block-level and system-level ASIC testbenches using Systemverilog
-Develop new ASIC verification environments to support ASIC development.
-Maintain existing ASIC verification environments.
-Define and develop application tests required to verify ASICs meet functional and performance goals.
-Define and implement functional/code coverage plans.
-Develop testing and regression methodologies for new verification flow.
-Develop/maintain/enhance environment tools/scripts/makefiles.