- Get the circuit netlist (nmos.netl file) and put it in the following link:
/student_lab/digital_ic/variant_val/...
- Input files necessary for simulation. For input files take: - Input slope: 50 ps and Output capacitive load value, Cload: 5 fF 1. The input file for defining the input characteristics of NMOS transistor in DC mode by using HSpice circuit simulation tool is listed below: *NNOS Transistor *Input Characteristics * HSPICE Netlist .options POST=1 parhier=local * Models section * Include models .include '/student_lab/digital_ic/all_models/model_val' * Design variables section * Define parameters .param vdd = VDD_val .temp Temp_val * Structural netlist section .include '/student_lab/digital_ic/variant_val/nmos.netl' vvss vss gnd dc=0 vvdd vdd vss dc='vdd' vbulk bulk vss dc=0 vin in vss dc=0 r1 out vdd 1k * Analysis section * DC Analyses .dc vin 0 vdd 0.01 .probe
v(*) i(*) *Options
.option post probe .end |
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