JD: asic Verification Engineer
Responsibilities:
1. Perform ASIC verification for large, complex high-speed ASICs for Exar's next generation products. 2. Develop detailed test plans, block and system-level test benches, reference models and verification environments. Achieve complete coverage to ensure first working silicon.
3. Develop functional models for System level architectural validation.
4. Assist in ASIC and system bring-up.
Requirement:
1. 4+ years of hands-on design verification experience in ASIC product development
2. Strong C/C++ software development experience
3. 3+ years of Experience in verilog, scripting (perl, etc.)
4. 1+ years of Experience in SystemVerilog and VMM
5. Knowledge of Network, IPsec and Encryption/Decryption algorithm is preferred
6. Strong problem solving skills, and attention to details
7. Good interpersonal skills (verbal and written)
8. An organized, enthusiastic self-starter, strong interest in hardware verification methodologies
9. Capable of working as an independent contributor and team member
JD: ASIC Design Engineer
Responsibilities:
1. Define block level micro-architecture and write workbook.
2. Evaluate block level performance, area and power.
3. Work on RTL coding, power reduction, synthesis, and static timing analysis.
4. Work closely with the architecture, verification, and integration team in solving design and implementation problems
5. System emulation and bring-up on FPGA prototype
Requirement:
1. Above 2 years relative experience
2. Master or Bachelor degree in Electrical Engineering or Computer Engineering
3. Knowledge of chip design and verification tools
4. Good understanding of the chip design flow and process.
5. Good logic design skills and Verilog hdl coding experience
6. Experience on synthesis, timing analysis, formal verification and floor-plan
7. Good English read, written skill, good oral skill is a plus
8. Self-motivated, integrity, and initiative
9. Good teamwork and communication skills.
JD: Senior Software Engineer
Responsibilities:
Act as senior developer to support security network (HIPP series) or storage (VTL) product lines, and develop new features or new products. Which covers:
1. Ramp up quickly on existing product lines, understand the code package, documentation, product status and scope.
2. Solving customer issues and reported bugs, add in new features if required.
3. Cooperation with marketing, AE, and develop team on reported issue/bug, give quick response and effective solution.
4. Follow up product line evolvement, and take part in next generation product design and development.
Requirement:
1. 5+ years c/c++ programming experience, excellent trouble shooting skills. Strong ability to identify, analyze and fix bug.
2. Self-motivated, actively accumulate knowledge of dedicated product line, day by day.
3. Excellent communication skills to co-work with cross-functional groups, ask first hand information and necessary support.
4. Familiar with linux programming is required.
5. Familiar with security protocol/technology (IPSEC, Encryption, Compression, Hash, etc) is desired.
6. Fluent read/write/verbal in English.
7. Bachelor degree of engineering is required.
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2011-2-22 11:03:19
楼主
。无奈顶下，不要见怪