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艾科嘉(杭州)信息技术有限公司,前身为赛安(杭州)微系统有限公司,是exar 在杭州的全资子公司。作为Exar重要的研发基地之一,艾科嘉专注于高端网络和信息安全芯片、加速和压缩板卡及其子系统的设计和开发。
艾科嘉将Ex (Excellence & Execution) C (Customer & Commitment) I (Integrity) T (Trust & Teamwork) E (Employees)作为公司文化,以平和、宽松的氛围追求高效率,高目标。目前艾科嘉团队拥有成员80余名,其中65%以上拥有硕士及以上学历,更有数名海外专家带领我们深入了解业内顶尖技术。
我们期待更多优秀人才加入艾科嘉,成就事业!
JD: Senior ASIC Verification Engineer
Responsibilities:
1.Perform ASIC verification for large, complex high-speed ASICs for Exar's next generation products.
2.Develop detailed test plans, block and system-level test benches, reference models and verification environments. Achieve complete coverage to ensure first working silicon.
3.Develop functional models for System level architectural validation.
4.Assist in ASIC and system bring-up.
QUALIFICATIONS: (please rank in order of necessity)
1. 4+ years of hands-on design verification experience in ASIC product development
2. Strong C/C++ software development experience
3. 3+ years of Experience in Verilog, scripting (perl, etc.)
4. 1+ years of Experience in SystemVerilog and VMM
5. Knowledge of Network, IPsec and Encryption/Decryption algorithm is preferred
6. Strong problem solving skills, and attention to details
7. Good interpersonal skills (verbal and written)
8. An organized, enthusiastic self-starter, strong interest in hardware verification methodologies
9.Capable of working as an independent contributor and team member
Job title: Logic Design Engineer
Job Description:
1. Define block level micro-architecture and write workbook.
2. Evaluate block level performance, area and power.
3. Work on RTL coding, power reduction, synthesis, and static timing analysis.
4. Work closely with the architecture, verification, and integration team in solving design and implementation problems
5. System emulation and bring-up on FPGA prototype
Responsibilities:
1. Above 2 years relative experience
2. Master or Bachelor degree in Electrical Engineering or Computer Engineering
3. Knowledge of chip design and verification tools
4. Good understanding of the chip design flow and process.
5. Good logic design skills and Verilog HDL coding experience
6. Experience on synthesis, timing analysis, formal verification and floor-plan
7. Good English read, written skill, good oral skill is a plus
8. Self-motivated, integrity, and initiative
9. Good teamwork and communication skills.
Job title: Senior Software Engineer
Responsibilities:
Act as senior developer to support security network (HIPP series) or storage (VTL) product lines, and develop new features or new products. Which covers:
1. Ramp up quickly on existing product lines, understand the code package, documentation, product status and scope.
2. Solving customer issues and reported bugs, add in new features if required.
3. Cooperation with marketing, AE, and develop team on reported issue/bug, give quick response and effective solution.
4. Follow up product line evolvement, and take part in next generation product design and development.
Requirement:
1. 5+ years c/c++ programming experience, excellent trouble shooting skills. Strong ability to identify, analyze and fix bug thoroughly.
2. Self-motivated, actively accumulate knowledge of dedicated product line, day by day.
3. Excellent communication skills to co-work with cross-functional groups, ask first hand information and necessary support.
4. Familiar with linux programming is required.
5. Familiar with security protocol/technology (IPSEC, Encryption, Compression, Hash, etc) is desired.
6. Fluent read/write/verbal in English.
7. Bachelor degree of engineering is required. |
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