An Engineer's Guide to Automated Testing of High-Speed Interfaces

drjiachen

An Engineer's Guide to Automated Testing of High-Speed Interfaces (Artech House Microwave Library)
byJose Moreira

Product DetailsISBN: 9781607839835
Author: Moreira, Jose
Publisher: Artech House Publishers
Author: Werkmann, Hubert
Subject: Electricity Publication
Date: August 2010
Binding: Hardcover
Language: English
Pages: 425

Synopses & ReviewsBook News Annotation:Moreira and Werkmann, both engineers with Verigy, a leading manufacturer of Automated Test Equipment (ATE), present this definitive guide to testing high-speed interfaces in electronics manufacturing. Beginning with an overview of the technology and high speed interface standards, and progressing through test design, instrumentation, production testing and advanced ATE topics, the work explains detailed and complicated processes with frequent illustrations and clear, easy to read text. Nine appendicies explore useful remedial information not directly related to ATE. Annotation ©2010 Book News, Inc., Portland, OR (booknews.com)
Synopsis providing a complete introduction to the state-of-the-art in high-speed digital testing with automated test equipment (ATE), this practical resourceis the first book to focus exclusively on this increasingly important topic. Featuring clear examples, this one stop reference covers all critical aspects of the subject, from high-speed digital basics, ATE instrumentation for digital applications, and test and measurements. to production testing, support instrumention and text fixture design. This in-depth volume also discusses advanced ATE topics, such as multiplexing of ATE pin channelsand testing of high-speed bi-directional interfaces with fly-by approaches

mtwumtwu

where it the book

xlteam11

good!. you 've got to read it

iseesky

good!thanks!
where is the book?

vertyang

http://www.rapid4search.com/files/1607839830
http://www.rapid4search.com/files/An_Engineer_s_Guide_to_Automated_Testing_of_High_Speed_Interfaces

vertyang

Table Of Contentsreface  xvii  
1 Introduction
  1 (8)
1.1 Characterization and Design Verification
  2 (2)
1.2 Production Testing
  4 (1)
1.3 Accuracy and Correlation
  5 (1)
1.4 The ATE Test Fixture
  5 (2)
1.5 The Future
  7 (2)
References
  7 (2)
2 High-Speed Digital Basics
  9 (46)
2.1 High-Speed Digital Signaling
  9 (8)
2.1.1 Out-of-Band Signaling
  10 (1)
2.1.2 Data Eye Diagram
  11 (1)
2.1.3 Differential Signaling
  12 (2)
2.1.4 Transmission Line Termination
  14 (3)
2.2 Time and Frequency Domains
  17 (4)
2.2.1 The Concept of Bandwidth and Its Pitfalls
  18 (3)
2.3 Bit Error Rate
  21 (2)
2.4 Jitter
  23 (16)
2.4.1 Jitter Histogram
  25 (1)
2.4.2 Jitter Categorization
  26 (8)
2.4.3 Amplitude Noise and Conversion to Timing Jitter
  34 (2)
2.4.4 Jitter in the Frequency Domain
  36 (3)
2.5 Classification of High-Speed I/O Interfaces
  39 (4)
2.6 Hardware Building Blocks and Concepts
  43 (12)
2.6.1 Phase Locked Loop (PLL)
  43 (3)
2.6.2 Delay Locked Loop (DLL)
  46 (1)
2.6.3 Clock and Data Recovery (CDR)
  46 (3)
2.6.4 Pre-Emphasis/De-Emphasis and Equalization
  49 (4)
References
  53 (2)
3 High-Speed Interface Standards
  55 (78)
3.1 PCI Express
  56 (17)
3.1.1 Application Areas
  56 (1)
3.1.2 PCI Express Fundamentals
  56 (3)
3.1.3 PCI Express Details
  59 (2)
3.1.4 PCI Express Protocol
  61 (4)
3.1.5 Electrical Specifications
  65 (3)
3.1.6 ATE Test Requirements
  68 (2)
3.1.7 Test Support
  70 (1)
3.1.8 Test Challenges
  71 (2)
3.2 Hyper Transport
  73 (20)
3.2.1 Application Areas
  73 (1)
3.2.2 Hyper Transport Protocol
  74 (9)
3.2.3 Electrical Specifications
  83 (2)
3.2.4 Test Support
  85 (1)
3.2.5 Test Requirements
  85 (6)
3.2.6 Test Challenges
  91 (2)
3.3 XDR DRAM
  93 (14)
3.3.1 Application Areas
  93 (1)
3.3.2 XDR Fundamentals
  93 (2)
3.3.3 XDR DRAM Details
  95 (4)
3.3.4 XDR Protocol
  99 (6)
3.3.5 Electrical Specifications
  105 (1)
3.3.6 ATE Test Requirements
  106 (1)
3.3.7 Test Support
  106 (1)
3.3.8 Test Challenges
  106 (1)
3.4 GDDR SDRAM
  107 (20)
3.4.1 Application Areas
  107 (1)
3.4.2 GDDR Fundamentals
  107 (1)
3.4.3 GDDR5 Details
  108 (6)
3.4.4 GDDR5 Protocol
  114 (8)
3.4.5 Electrical Specifications
  122 (1)
3.4.6 ATE Test Requirements
  123 (1)
3.4.7 Test Support
  124 (1)
3.4.8 Test Challenges
  124 (3)
3.5 Other High-Speed Digital Interface Standards
  127 (6)
References
  129 (4)
4 ATE Instrumentation for Digital Applications
  133 (30)
4.1 Digital Pin Electronics ATE Card
  137 (13)
4.1.1 CDR and Phase Tracking
  139 (1)
4.1.2 Equalization
  140 (1)
4.1.3 Time Interval Analyzer or Time Stamper
  140 (1)
4.1.4 Timing Jitter Injection
  141 (2)
4.1.5 Amplitude Noise and Common Mode Voltage Injection
  143 (1)
4.1.6 Bidirectional and Simultaneous Bidirectional Support
  144 (2)
4.1.7 Protocol Engine
  146 (1)
4.1.8 ATE Loopback Path
  146 (1)
4.1.9 Parametric Measurements
  146 (4)
4.2 Sampler/Digitizer ATE Card
  150 (3)
4.2.1 Aliasing
  150 (1)
4.2.2 Digitizer
  151 (1)
4.2.3 Sampler
  152 (1)
4.3 Parametric Measurements with Sampled Data
  153 (7)
4.3.1 Undersampling of High-Speed I/O Signals
  153 (2)
4.3.2 Coherency Equation
  155 (1)
4.3.3 Capturing Digital Waveforms
  156 (3)
4.3.4 Special Considerations for Coherent Sampling with Digital ATE Channels
  159 (1)
4.4 Power Supplies
  160 (3)
References
  162 (1)
5 Tests and Measurements
  163 (74)
5.1 Bit and Pattern Alignment
  163 (7)
5.1.1 Bit Alignment
  165 (3)
5.1.2 Pattern Alignment
  168 (2)
5.2 Functional Test
  170 (2)
5.3 Shmoo Tests
  172 (3)
5.4 Fundamental Driver Tests
  175 (17)
5.4.1 Rise/Fall Time
  175 (1)
5.4.2 Data Eye Diagram
  176 (9)
5.4.3 BER Bathtub Curve
  185 (3)
5.4.4 Skew
  188 (3)
5.4.5 Pre-Emphasis and De-Emphasis Measurement
  191 (1)
5.5 Driver Jitter Tests
  192 (19)
5.5.1 Jitter Histogram
  192 (1)
5.5.2 RMS Jitter
  193 (1)
5.5.3 Peak-to-Peak Jitter
  194 (1)
5.5.4 Measuring the Jitter Spectrum
  195 (2)
5.5.5 Random and Deterministic Jitter Separation
  197 (7)
5.5.6 Measuring the Data Dependent Jitter
  204 (1)
5.5.7 Jitter Measurement Correlation
  205 (3)
5.5.8 Driver Amplitude Noise
  208 (3)
5.6 Fundamental Receiver Tests
  211 (3)
5.6.1 Setup and Hold
  211 (1)
5.6.2 Receiver Sensitivity
  212 (2)
5.7 Receiver Jitter Tolerance
  214 (7)
5.7.1 Random Jitter Tolerance
  215 (1)
5.7.2 Sinusoidal Jitter Tolerance
  216 (2)
5.7.3 DDJ Jitter Tolerance
  218 (2)
5.7.4 Testing the Receiver Equalizer
  220 (1)
5.8 PLL Characterization
  221 (6)
5.8.1 Jitter Transfer
  221 (2)
5.8.2 Frequency Offset
  223 (1)
5.8.3 Spread Spectrum Clocking
  224 (3)
5.9 Other Tests
  227 (6)
5.9.1 Impedance Tests
  227 (4)
5.9.2 Return Loss
  231 (2)
5.10 Measurement Errors
  233 (4)
References
  234 (3)
6 Production Testing
  237 (32)
6.1 Golden Device
  238 (1)
6.2 System Level Test
  239 (1)
6.3 Instrument-Based Testing: At-Speed ATE
  239 (7)
6.3.1 Physical Implementation
  240 (2)
6.3.2 Parametric Testing
  242 (4)
6.4 Instrument-Based Testing: Low-Speed ATE
  246 (15)
6.4.1 Double Data Clocking
  246 (3)
6.4.2 Channel Multiplexing
  249 (1)
6.4.3 Near-End Loopback Testing
  249 (12)
6.5 Instrument-Based Testing: Bench Instrumentation
  261 (1)
6.6 Active Test Fixture
  261 (1)
6.7 Multisite Testing
  262 (7)
6.7.1 Driver Sharing for Multisite Applications
  263 (3)
References
  266 (3)
7 Support Instrumentation
  269 (42)
7.1 Oscilloscopes
  269 (5)
7.1.1 Real-Time Oscilloscopes
  269 (1)
7.1.2 Equivalent-Time Sampling Oscilloscopes
  270 (4)
7.2 Bit Error Rate Tester
  274 (1)
7.3 Time Interval Analyzer
  275 (1)
7.4 Spectrum Analyzer
  276 (1)
7.5 Vector Network Analyzer
  277 (1)
7.6 Arbitrary Waveform and Function Generators
  277 (2)
7.7 Noise Generators
  279 (1)
7.8 Sinusoidal Clock Sources
  280 (2)
7.9 Connecting Bench Instrumentation to an ATE System
  282 (5)
7.9.1 Signal Integrity
  282 (2)
7.9.2 Synchronization
  284 (2)
7.9.3 External Reference Clock Impact on Jitter Measurements
  286 (1)
7.10 Coaxial Cables and Connectors
  287 (11)
7.10.1 Coaxial Cables
  287 (6)
7.10.2 Coaxial Connectors
  293 (5)
7.11 Accessories
  298 (13)
7.11.1 Power Splitters and Power Dividers/Combiners
  298 (1)
7.11.2 Attenuators, Blocking Capacitors, and Terminations
  299 (2)
7.11.3 Pick-Off T
  301 (1)
7.11.4 Delay Lines
  302 (1)
7.11.5 Probes
  302 (4)
7.11.6 Balun
  306 (2)
7.11.7 Rise Time Converters
  308 (1)
References
  309 (2)
8 Test Fixture Design
  311 (80)
8.1 Test Fixtures
  313 (2)
8.2 High-Speed Design Effects
  315 (15)
8.2.1 Reflections Due to Impedance Mismatches
  316 (3)
8.2.2 Conductor Losses
  319 (1)
8.2.3 Dielectric Losses
  320 (8)
8.2.4 Crosstalk
  328 (2)
8.3 Impedance Controlled Routing
  330 (4)
8.3.1 Microstrip and Striplines
  330 (3)
8.3.2 Differential Routing
  333 (1)
8.4 Via Transitions
  334 (8)
8.4.1 Interlayer Vias
  339 (1)
8.4.2 Pogo Pin Vias
  340 (2)
8.5 DUT BGA Ballout
  342 (4)
8.6 Sockets
  346 (3)
8.6.1 Socket Electrical Characterization
  347 (2)
8.7 Relays
  349 (5)
8.8 Bidirectional Layout
  354 (2)
8.9 Wafer Probing
  356 (3)
8.10 Stack-Up
  359 (4)
8.11 Power Distribution Network
  363 (28)
8.11.1 Power Planes
  370 (5)
8.11.2 Decoupling Capacitors
  375 (8)
8.11.3 Socket Inductance
  383 (1)
8.11.4 Power Distribution Network Design
  384 (1)
8.11.5 Power Distribution Network Simulation
  384 (2)
References
  386 (5)
9 Advanced ATE Topics
  391 (58)
9.1 ATE Specifications and Calibration
  391 (8)
9.1.1 Accuracy and Resolution
  391 (1)
9.1.2 Understanding OTA and EPA
  392 (1)
9.1.3 Linearity and Edge Placement Accuracy
  393 (2)
9.1.4 Calibration
  395 (4)
9.2 Multiplexing of ATE Channels
  399 (2)
9.3 Focus Calibration
  401 (8)
9.3.1 Skew Calibration
  402 (1)
9.3.2 Data Eye Height Calibration
  402 (2)
9.3.3 Jitter Injection
  404 (2)
9.3.4 Data Eye Profile
  406 (3)
9.4 Testing of High-Speed Bidirectional Interfaces with a Dual Transmission Line Approach
  409 (5)
9.5 Including the DUT Receiver Data Recovery in Driver Tests
  414 (2)
9.6 Protocol Awareness and Protocol-Based Testing
  416 (5)
9.7 Testing Multilevel Interfaces with Standard Digital ATE Pin Electronics
  421 (2)
9.8 Signal Path Characterization and Compensation
  423 (16)
9.8.1 Signal Path Loss Compensation: De-Embedding
  423 (5)
9.8.2 Characterization in the Frequency Domain
  428 (2)
9.8.3 Signal Path Loss Compensation: Equalization
  430 (9)
9.9 ATE DC Level Adjustments
  439 (10)
9.9.1 Correction of Force Levels for DUT Input Pins
  441 (1)
9.9.2 Correction of Levels for DUT Output Pins
  442 (3)
References
  445 (4)
A Introduction to the Gaussian Distribution and Analytical Computation of the BER
  449 (12)
A.1 The Gaussian Distribution
  450 (3)
A.2 Computation of the BER for a System with Only Gaussian Random Jitter
  453 (3)
A.3 Computation of the α(BER) Value
  456 (2)
A.4 Properties of the Error Function erf(x) and Complementary Error Function erfc(x)
  458 (3)
References
  459 (2)
B The Dual Dirac Model and RJ/DJ Separation
  461 (8)
B.1 The Dual Dirac Jitter Model
  461 (4)
B.2 RJ/DJ Separation with the Q-Factor Algorithm
  465 (4)
References
  467 (2)
C Pseudo-Random Bit Sequences and Other Data Patterns
  469 (6)
C.1 Pseudo-Random Bit Sequences
  469 (1)
C.2 Pseudo-Random Word Sequences
  470 (2)
C.3 Other Important Patterns
  472 (3)
References
  473 (2)
D Coding, Scrambling, Disparity, and CRC
  475 (16)
D.1 Disparity
  476 (2)
D.2 8B/10B Coding
  478 (3)
D.3 Scrambling
  481 (3)
D.4 Error Detection
  484 (7)
D.4.1 Parity Bits
  485 (1)
D.4.2 Checksums
  485 (3)
References
  488 (3)
E Time Domain Reflectometry and Time Domain Transmission (TDR/TDT)
  491 (12)
E.1 TDR
  492 (5)
E.1.1 Measuring the Impedance of a Trace with a TDR
  493 (1)
E.1.2 Measuring the Round-Trip Delay of a Signal Trace
  494 (1)
E.1.3 Measuring Discontinuities on a Signal Path with a TDR
  495 (1)
E.1.4 Measuring the Return Loss with a TDR
  495 (2)
E.2 TDT
  497 (2)
E.2.1 Measuring the Step Response
  497 (1)
E.2.2 Measuring the Insertion Loss with a TDT
  498 (1)
E.2.3 Measuring Crosstalk Using a TDT and an Extra Sampler
  498 (1)
E.3 Differential TDR/TDT Measurements
  499 (4)
References
  501 (2)
F S-Parameters
  503 (12)
F.1 Simulating and Synthesizing Time-Domain Responses from S-Parameters
  509 (2)
F.2 S-Parameters of Coupled Differential Pairs and Structures
  511 (4)
References
  513 (2)
G Engineering CAD Tools
  515 (10)
G.1 Circuit Simulators
  515 (3)
G.2 3D EM Field Solvers
  518 (1)
G.3 2D Planar Field Solvers
  518 (2)
G.4 Power Integrity
  520 (1)
G.5 Model Generation
  521 (1)
G.6 Other Tools
  521 (4)
References
  524 (1)
H Test Fixture Evaluation and Characterization
  525 (18)
H.1 Measuring the Test Fixture Performance
  525 (10)
H.1.1 Test Coupons
  527 (2)
H.1.2 Test Fixture Socket and Socket Via Field Probing
  529 (6)
H.2 Measuring the Test Fixture Power Distribution Network
  535 (8)
References
  540 (3)
I Jitter Injection Calibration
  543 (16)
I.1 Sinusoidal Jitter Injection Calibration
  543 (8)
I.1.1 The J1/J0 Bessel Approach
  544 (4)
I.1.2 The RJ Subtraction Approach
  548 (3)
I.2 Random Jitter Injection Calibration
  551 (4)
I.3 ISI Jitter Injection Calibration
  555 (4)
References
  557 (2)
About the Authors  559 (2)
Index  561

tempxyz

楼上的朋友，能够分享一下吗？

vertyang

我也没有电子版啊

tempxyz

支持一下！同求

fei2000

什么时候有电子版的呀