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Requirement:
1. Masters/Bachelor’s Degree in Electrical/Electronics Engineering or in related field
2. Tool skills: Synopsys Design Compiler, PERL, TCL languages, Prime Time and constraint creation/modification
3. Familiar with DFT flow.
4. Good working knowledge of VHDL and/or Verilog
5. Minimum 2 years of synthesis and timing closure experience
6. Successful synthesis experience for a least one successful tape out project
Job Scope:
1. Writing, running, optimization of logic synthesis scripts
2. In-depth knowledge of STA. Ability to handle timing analysis for multiple modes and corners
3. Physical design Floor planning, clock tree synthesis, routing cleanup
4. Formal Verification (Equivalence checking)
5. Physical Verification (DRC, ERC, LVS)
6. IP merge interfacing with floorplan and place&route team.
7. Be involved in evaluating packaging options for the ASIC.
8. Working and communication interface with layout group |
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发表于 2010-11-19 11:12:31
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