OPENJTAG hardware

MEMS_dream

The OPENJTAG hardware uses the MAX II EPM570 CPLD from Altera as serializer, and
the FT245BM from FTDI Chips as USB FIFO. The circuit is simple an easy to understand.
The FT245BM is the USB front end from the PC and the CPLD, bringing an easy and
cheap solution to communicate with the target hardware. The EPM570 selection is
because Altera has not another device with a minor pin count and enough capacity. You
can see that the half device –a whole bank- is unused. The  OPENJTAG hardware is
powered from the USB power supply, using a LK112M33TR regulator to supply the
internal 3.3V 140mA.
All the JTAG output pins are buffered by two MAX3378E from Maxim. This bi-directional
level translators isolates the  OPENJTAG hardware from the target device. The
OPENJTAG hardware uses 3.3V as I/O power, but the target hardware could use a
diverse power supply, as 1.2V, 1.8V, 2.5V, 3.3V or 5V. The half-part of the MAX3378E –
the target side- is powered directly from the target I/O power supply.
The CPLD uses a 48MHZ crystal oscillator as the main clock supply. The shifter uses two
clock pulses to output the TCK signal, then the maximum clock frequency to drive TCK will
be 24MHZ.
Also, the OPENJTAG hardware has a 8 non protected user I/O pins to expand the board
capabilities. The board have two JTAG connectors: J5 is the JTAG cable to communicate
with the target device, and J3 is the JTAG cable to program the internal EPM570 CPLD.