外资公司需要高级/staff芯片验证人才

susan1117

Job Title:	Sr/Staff Verification Engineer
Post Holder:
Reports To:	Sr. Manager, MFS Verification
Direct Reports:	0
No. of Indirect Reports:	0
Key Relationships (internal and external):	Internal: IC Design, System Hardware, PM External: EDA company
Revenue / Budgetary Responsibility (where relevant):	0
Function:	Engineering
Location:	Shanghai

Job Purpose:
Take the lead role developing verification methodology, verification plan for SoC chips. And execute on the verification plan, achieving the best functional coverage.
Key Responsibilities:
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Own multiple modules, sub-systems, create constrained random based, coverage targeted verification plan and verify them from unit level going towards chip level integration.
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Own 3rd party IP verification/validation -- verify and validate them at unit, chip and system level.
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Help automate verification/validation tasks, run regression, manage bug tracking, run and analyze functional and code coverage, achieve coverage goals, etc.
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Support gate-level net-list functional and timing verification activities till tapeout.
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Conduct pre-silicon validation on a FPGA platform.
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Support test pattern generation and debugging for ATE testing.


Person Specification:

Required:	Desired:
Minimum 5 year of industry experience, minimum MS degree in Electrical/Computer engineering or equivalent. In-depth knowledge of SoC/ASIC verification flow with emphasis in coverage driven verification/validation methodology. Clear understanding of constrained random verification process, functional coverage, code coverage, assertion methodology and their philosophies. Track record of picking up legacy verification environment and work on fully developed DV environment, as well as, developing DV environment from scratch. In depth knowledge of ARM Instruction set and AMBA bus architecture. Knowledge of C, assembly for ARM processor. Intricate knowledge of Verilog, Verilog simulator and debug process. Have hands-on experience on crafting complex verification environment with industry standard HVL based methodology (must have SystemC, SysVerilog, vera, or Specman-e based experience).	Track record of delivering multiple fully verified chips from concepts to tapeout. Depth and breadth of knowledge on industry standard IO protocols: SPI, I2C, I2S, flash memories, SRAM and DRAM.

susan1117

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