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[招聘] 芯片设计和验证职位请进

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发表于 2010-7-23 11:27:36 | 显示全部楼层 |阅读模式

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先来第一个职位,职位名称:Staff Engineer, PSV,主要是做SI方向的。工作地点在上海浦东,
有意向者可以联系Susan.1817@hotmail.com

Key Responsibilities:
  • High speed interface design and debug in whole flow, such as 400Mhz DDR3 interface
  • Drive the high speed interface technology in company
  • SoC post-silicon verification
  • SoC stability and compatibility testing
  • SoC performance tuning
  • Conduct SoC testing and inspection to ensure and improve product stability
  • Problems solving in SoC testing
Person Specification:
Required:
Desired:
·
Education: Bachelor or higher degrees in electronics, computer, electrical engineering or related fields

·
Experience: 5+ years in SoC testing or verification, special in high speed interface

·
Experience in the development of SoC test plan, test cases, and test application (optional)

·
Familiar with boot-loader and software development and modification (optional)

·
Familiar with ARM assembly language and C program language (optional)

·
Good team work

·
Good communication skill

·
Patience and diplomacy

·
High speed interface debug and design experience(SI and PI analysis, special for high speed DDR interface)

·
Hardware debug and design experience (prefer)

·
WinCE or Linux kernel develop experience (optional)










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发表于 2010-7-23 12:45:21 | 显示全部楼层
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发表于 2010-7-23 12:46:33 | 显示全部楼层
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发表于 2010-7-23 12:47:59 | 显示全部楼层
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 楼主| 发表于 2010-7-23 15:29:29 | 显示全部楼层
恩 谢谢顶
 楼主| 发表于 2010-7-23 15:31:01 | 显示全部楼层
本帖最后由 susan1117 于 2010-7-23 15:33 编辑

senior or staff verification engineer

Job Purpose:
Take the lead role developing verification methodology, verification plan for SoC chips. And execute on the verification plan, achieving the best functional coverage.
Key Responsibilities:
•        Own multiple modules, sub-systems, create constrained random based, coverage targeted verification plan and verify them from unit level going towards chip level integration.
•        Own 3rd party IP verification/validation -- verify and validate them at unit, chip and system level.
•        Help automate verification/validation tasks, run regression, manage bug tracking, run and analyze functional and code coverage, achieve coverage goals, etc.
•        Support gate-level net-list functional and timing verification activities till tapeout.
•        Conduct pre-silicon validation on a FPGA platform.
•        Support test pattern generation and debugging for ATE testing.
Person Specification:
Required:        Desired:
•        Minimum 5 year of industry experience, minimum MS degree in Electrical/Computer engineering or equivalent.
•        In-depth knowledge of SoC/ASIC verification flow with emphasis in coverage driven verification/validation methodology.
•        Clear understanding of constrained random verification process, functional coverage, code coverage, assertion methodology and their philosophies.
•        Track record of picking up legacy verification environment and work on fully developed DV environment, as well as, developing DV environment from scratch.
•        In depth knowledge of ARM Instruction set and AMBA bus architecture.
•        Knowledge of C, assembly for ARM processor.
•        Intricate knowledge of Verilog, Verilog simulator and debug process.
•        Have hands-on experience on crafting complex verification environment with industry standard HVL based methodology (must have SystemC, SysVerilog, vera, or Specman-e based experience).

        •        Track record of delivering multiple fully verified chips from concepts to tapeout.
•        Depth and breadth of knowledge on industry standard IO protocols: SPI, I2C, I2S, flash memories, SRAM and DRAM.
发表于 2010-7-24 21:19:33 | 显示全部楼层
 楼主| 发表于 2010-7-26 14:01:17 | 显示全部楼层
自己顶一下
发表于 2010-7-29 09:47:43 | 显示全部楼层
要招版图的吗
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