ABSTRACT
With the ability to integrate a large number of cores on a single chip, research into on-chip networks
to facilitate communication becomes increasingly important. On-chip networks seek to provide a
scalable and high-bandwidth communication substrate for multi-core and many-core architectures.
High bandwidth and low latency within the on-chip network must be achieved while fitting within
tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip
network design and provide the reader with an overview of the current state-of-the-art research in
this field.
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2010-9-5 23:43:24
