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部门现在急需两三个高级验证工程师，待遇从优.
五年以上工作经验，熟练C/C++, System Verilog, VMM.
有USB 1.0/2.0/3.0, SATA验证经验的优先考虑。
有合适的尽快把简历给我吧,谢谢。（合适的我会给你回信的 ）
yong1.chen@amd.com
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION :
We are currently looking for an Senior Eng Design Verification Engineer who will be
responsible for all aspects of verification on next generation integrated processors chipset,
including developing DV infrastructure environment, testbenches, modeling,
assertions/checkers/monitors, test plan & test development, regressions, and
infrastructure development. Responsibility includes participating in the pre-silicon blocks,
chip, multi-chip and system level verification strategy:
- Verification of Graphic North Bridge design using complex DV environment C/C++,
SystemVeilog, OVM, SystemC, Verilog - Infrastructure development
- Experience in use of front end CAD tools Synopsys (VCS, )
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled, multiple sites North
America and Asia
- Flexible in terms of responsibilities and hours.
PREFERRED EXPERIENCE:
- Bachelor/Master in Electrical/Computer Engineering.
- Strong C and C++ software development and scripting languages (Perl, C Shell,
Makefile, …) experience.
- Good knowledge of SystemVerilog and OVM is desirable.
- 3+ years experience in Verification in a large scale ASIC design environment.
- Strong background with hardware verification methodologies such as coverage-based
verification methodology with the use of hardware assertions (PSL or SVA).
- Strong analytical thinking skills, excellent attention to detail, and good coding skills
are required.
- Must be organized, enthusiastic self-starter and have good communication skills and
the ability and desire to work as a team. |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2010-5-26 17:44:47
楼主
顶。。。。