英国顺卓急招IC设计工程师6名

lanny928

Positions: Physical implementation Engineers
Type: Full time
Email: recruitment.china@sondrel.com
Location: Shanghai and Xi’an
Multiple vacancies: Physical Design Engineer / Project Manager
Due to the expansion of our Chinese design centres in Xi’an and Shanghai, Europe's leading design service company has multiple vacancies for senior physical design engineers / project managers with particular experience in timing closure, place and route, DFT, floor planning, in 90nm and below SoC design.

Company Introduction
Sondrel is Europe’s leading IC consulting company, with offices in the UK, France, Italy and Israel. Since 2002, our flexible pool of experienced design experts have worked with both startups and major semiconductor companies in a broad range of markets. Sondrel engineers have completed over 140 designs, including many that target 90nm, 65nm and 45nm process geometries. In September 2008, Sondrel established its first design service center in China and is now seeking to expand its silicon team. Whilst multi-skilled individuals are highly valued within the team, there are also opportunities for those with specific areas of expertise and varying levels of experience. As part of a rapidly expanding team in a young company, these roles will provide exciting career development opportunities to the right applicants.
We are looking for motivated and experienced individuals who are able to work independently and within a team environment. Tasks to be executed include all those from synthesis through place and route to tape-out. Therefore the right candidates will have extensive experience in back end design including timing analysis, floor planning, timing closure, physical verification, and ideally, design for test.

Experience
Some experience in physical design engineering coupled with a good degree

Essential skills
The successful applicants will need experience in at least some of the following areas:

Digital Soc chip design and implementation Design automation and analysis using scripting languages, particular Tcl and Perl Design Flows and the EDA tools, in particular tools from Magma, Mentor and Synopsys. Experience with tools from Apache and Azuro would be an advantage Sign-off methodology and EDA tools for STA, Noise, Power, etc. Structured design styles involving placed gates
• ATPG tools and methodologies.

Key Responsibilities
Depending on experience, key responsibilities will involve some of the following:

Development and optimisation of high performance and low power Soc physical implementation methodology Working with European engineers to do block level and full chip floor planning, timing and power analysis, and P&R
• Design consulting in customer’s offices on physical implementation tasks

Interfacing with foundry and IP providers on IP imp

lanny928

顶置，顶置！

lanny928

继续顶置吧

lanny928

顶置， 希望大家踊跃报名！

123231

好，真好！有这样的多发点！