上海IC公司内部推荐

lyu

Atheros
验证人员
工作2-5年都可以，
最好有specman，vera或者vmm相关经验

设计人员也有招聘。
email：albert_lei@yeah.net

nowich

谢谢发布~~

ksj116

请问，是哪个方面的设计人员在招聘？？、

lyu

ASIC Design Engineer . Shanghai
QUALIFICATION (DETAIL):
Education:

BS in Electrical/Electronics Engineering, MS preferred.
Experience:

.. 3 years experience with Verilog programming, logic synthesis and gate
timing. A proven record of delivering successful ASIC's to the market is
preferred.

.. One or more advantages as following are highly desirable: A strong
background in digital communication, signal processing and networking
protocols; IC Design experiences in wireless communications and audio
processing; Experiences with ARM/DSP, AHB bus and External interface
development.

.. Good communication skills in English.

.. Experience in Bluetooth chip design a plus

.. Must be proficient in RTL coding, logic synthesis, gate-level simulations.

.. Good knowledge of IC design backend flows.

.. Experiences in IC life-cycle from conception, design, verification,
top-level netlist with pads to tape-out, chip-testing and mass-production.

.. FPGA, PCB or embedded SW skill is a plus.
DESCRIPTION OF FUNCTION & RESPONSIBILITY:
The Digital Design Engineer will be responsible for designing our wireless and
SOC ASIC's. You will work closely with our architecture/algorithm engineers to
explore ideas for next generation products and then develop RTL to tern these
ideas into customer solutions.

.. Chip features specification and RTL design

.. Synthesis, verification, timing.

.. FPGA emulation, lab validation and debugging.

lyu

Digital Design Verification Engineer
DESCRIPTION OF FUNCTION & RESPONSIBILITY:

Develop reusable block-level and system-level ASIC testbenches using
Systemverilog

Develop new ASIC verification environments to support ASIC
development.

Maintain existing ASIC verification environments.

Define and develop application tests required to verify Asics meet
functional and performance goals.

Define and implement functional/code coverage plans.

Develop testing and regression methodologies for new verification flow.

Develop/maintain/enhance environment tools/scripts/makefiles.
EDUCATION:
Master's degree from first rate engineering schools is preferred.
EXPERIENCE:

Minimum of 3 years ASIC Verification experience in a product
development environment

Proven ASIC Design Verification skills

Rich experience with Specman or System Verilog

Digital verification experience on MIPS CPU/AXI/DDR Controller

Knowledge of data and telecommunication networking(IP/Ethernet)

Experience with one or more scripting languages: TCL, Perl, python

Superior debugging skills for large ASIC designs

Strong written and verbal communication skills

Adaptable to evolving customer requirement

igooo

帮你顶下啊