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本帖最后由 hi_china59 于 2010-4-3 21:37 编辑
Oscillation Control in CMOS Phase Locked Loops
TABLE OF CONTENTS
I INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 4
II PHASE-LOCKED LOOPS 6
2.1 Phase-Locked Loop Basics 6
2.2 Phase-Locked Loop Architectures 8
2.2.1 The Linear PLL 8
2.2.2 The Digital PLL 10
2.2.3 The All-Digital PLL 21
2.2.4 The Charge-Pump PLL 22
III OSCILLATION CONTROL IN CHARGE-PUMP PLLS 27
3.1 CMOS PFD Types and Comparison 28
3.1.1 The Conventional PFD 28
3.1.2 The PFDs with Improved D-Flip-Flops 30
3.1.3 The pt-PFD and the Modified pt-PFD 31
3.1.4 The nc-PFD 32
3.2 CMOS Charge Pump Types and Comparison 33
3.2.1 Single-ended Charge Pumps 34
3.2.2 Differential Charge Pumps 39
IV SINGLE-ENDED CONTROL FOR MULTI-GHz CPPLLs 44
4.1 Design of a Low-Noise 1.8 GHz CPPLL 44
4.1.1 Phase-Frequency Detector Design 44
4.1.2 Single-Ended Charge Pump Design 50
4.1.3 Differential Ring Oscillator with Single-Ended Control 53
4.1.4 Auxiliary Circuits 61
4.1.5 PLL Test Results 67
4.2 Design of a Low-Noise 5.8 GHz CPPLL 69
4.2.1 Ring Oscillator for Maximum Speed 69
4.2.2 PLL Test Results 74
V DIFFERENTIAL CONTROL FOR MULTI-GHz CPPLLs 76
5.1 Design of a CPPLL with Differential Control 77
5.1.1 Differential Charge Pump Design 77
5.1.2 LC Oscillator Design 83
5.1.3 PLL Test Results 91
5.2 Physical Design Considerations 95
VI PLL DESIGN SUMMARY 98
6.1 LC versus Ring Oscillators 98
6.2 Single-Ended versus Differential Oscillation Control 101
6.2 PLL Comparison
VII PULSE-STREAM CODED PHASE-LOCKED LOOPS 117
7.1 Digitization of the Oscillation Control 121
7.1.1 Dual Pulse-Train PFD 121
7.1.2 Single Pulse-Train PFD 122
7.2 A Simplified Pulse-Stream Coded PLL 123
7.3 Next Generation Pulse-Stream Coded PLL 131
7.3.1 Single Pulse-Train PFD Implementation 133
7.3.2 Truncated UP/DOWN Counter 150
7.3.3 DAC and CCO 155
7.3.4 Pulse-Stream Coded PLL Design Guidelines 157
VIII CONCLUSIONS AND FUTURE RESEARCH 163
8.1 Conclusions 163
8.2 Future Research 167
REFERENCES 170 |
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