[LSI]验证的盛宴--(Staff/Senior)Verification Engineer, Aug.20,2010

lowpowerdesign

LSI全球研发中心在徐汇区顶级写字楼（周边房价六七万吧），标准美资企业，Fabless大公司，工作环境优秀，团队气氛友好，团结向上,薪水也很不错，有较多出国培训机会，向上空间大，对职业生涯大有裨益，进来还发股票（最近）。如果有意，请发送简历到lowpowerdesign@hotmail.com.

顺便提一下内推和猎头。公司的每招聘猎头推荐的人才都要一定的费用，而内推却没有。同时，公司相关部门是有成本考核指标的。所以内推的录用率高。同时，把简历给猎头，简历的安全系数不高，送到老板手里就麻烦了：）本来这些东西我不想说的，因为这个版上猎头不少。不过貌似这是“众人皆知的秘密”.

这个职位是内推，可以提高您的录用几率，而且简历安全系数高啊，你懂的......

1. Verification Design Engineer--十年以上经验，当然你够牛，八年以上也可以--要求高，当然薪水也高啦
Responsible for Design, Verification and customer support of protocol

systems. Good knowledge of High Speed Interconnects, Storage and

Networking Protocols, such as PCI Express, Ethernet, Fibre Channel, Serial

RIO, Interlaken. Good communication skill is must.

Experience with FPGA prototyping/validation a plus.

PREFERRED EXPERIENCE:

Design skills:
- Micro-architecture development & RTL Design
- Synthesis & Timing analysis
Verification skills:
- Verification, including development of methodologies, test plans, compliance test suite, test bench & test cases, using System Verilog, Vera and Specman.
- Development of Bus Functional models (BFMs), transactors, assertions, and manage coverage and regressions
Standards development:
- Work with standards bodies such as IEEE and PCI SIG to develop industry standard specification for next generation product
Must be conversant with the following:
– Verilog, System Verilog, C++, EDA CAD tools,
– Synthesis, Timing constraints and Logic Equivalence
MSEE with 10+ years of relevant experience in a semiconductor industry.

2. Senior Verification Engineer--四年以上经验，求贤若渴啊！
Duties will include working with a Verification Team to develop reusable block and system level verification environment using high level verification language to support ASIC development.
Review RTL architectural and implementation specifications. Develop test plan, create stimulus drivers, monitors, reference models, scoreboards, protocol checkers to verify function and performance of advanced multiprotocol networking ASICs.
Define and develop application tests required to verify ASICs meet functional and performance goals.
Define and implement functional coverage plans.
Define and implement code coverage plans. Develop testing and regression
methodologies for new verification flow.
Coordinate test plan implementation and regressions with remote team.
Incorporate reusability into all aspects of the verification environment.
Develop/maintain/enhance environment tools/scripts/makefiles.
Functional/Industry Knowledge:
Required:
- Minimum of 4-6 years ASIC verification experience in a product development environment
- Proven ASIC Design Verification skills
- Proficient with high level verification languages such as System Verilog and Specman e.
- Knowledge of data and telecommunication networking
- Proficient with one or more scripting languages, such as Shell, Perl and TCL.
- Superior debugging skills for large ASIC designs
- Strong written and verbal communication skills
- Adaptable to evolving customer requirements
- Experience in a lead position giving guidance to other engineers, tracking and overseeing development progress.

3.Read Channel Verification Engineer --很实在的职位，需要概念清晰，有一定经验
Duties will include functional verification of Storage read channel mixed-signal IP.

Candidate will be expected to contribute to design and development

of System Verilog based verification environment and will be responsible for

verification closure of block/chip/system level functions for mixed signal based

IP. Experience with System Verilog and functional coverage methodologies are

required.
PREFERRED EXPERIENCE:
BSEE with 3-5+ years of design and/or verification experience required, MSEE preferred.
Required knowledge and skills:
- Expertise in System Verilog required
- Good understanding of Digital Signal Processing
- Good understanding of Analog and Digital Circuits
- Very good analytical/debugging skill
- Good verbal and written communication skills
Desirable skills:
- Knowledge of Verilog-AMS, Perl
- Knowledge of verification methodologies including functional coverage and constrained
random testing
- Knowledge of VLSI design flows & DFT
- Familiarity of high level programming language
- Experience working with globally distributed team

lowpowerdesign

要有项目经验

没有项目经验投简历也没有用，因为马上要做项目 1# lowpowerdesign

lowpowerdesign

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lowpowerdesign

顶！！

lowpowerdesign

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nicozj

路过帮顶啊

lowpowerdesign

路过帮顶啊
nicozj 发表于 2010-3-4 14:41

                               
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多谢啦：）

lowpowerdesign

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guang3000

有PLL做真好

lowpowerdesign

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