The Synplify Premier solution is the industry's most productive FPGA implementation and debug environment. It includes all the features of Synplify Pro and additionally provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting single FPGA-based prototypes.
The Synplify Premier software delivers fast turnaround time capabilities and feedback for users seeking to quickly implement the design on the board or to tune their design projects prior to final implementation. It addresses the most challenging aspects of FPGA design including timing closure and has the ability to perform graph-based physical synthesis for more accurate upfront timing prediction. It provides flows for fast logic verification and RT-Level debug. Under the hood, it contains optimization techniques that enhance DSP, IP and embedded design results. For ASIC prototypers, it delivers ASIC design file and DesignWare compatibility as well as tight integration with the Confirma Rapid Prototyping platform and FPGA vendor back-end tools as well as vendor embedded tools including Altera SoPC Builder and Xilinx EDK.
The Synplify Premier product offers FPGA Designers and ASIC Prototypers, targeting single FPGA-based prototypes, with the most efficient method of design implementation and debug. The Synplify Premier software provides in-system verification of FPGAs, dramatically accelerates the debug process, and provides a rapid and incremental method for finding elusive design problems.
The Synplify Premier software advantages include:
* technology and vendor independence
* in-system debug
* fast timing closure
* RTL analysis
* DSP-friendly synthesis algorithms
* superior Quality of Results (QoR)
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发表于 2010-2-11 11:24:51
