Static Timing Analysis for Nanometer Designs: A Practical Approach

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J. Bhasker, Rakesh Chadha, "Static Timing Analysis for Nanometer Designs: A Practical Approach"  
Springer | 2009 | ISBN: 0387938192 | 572 pages | PDF | 13,4 MB

The book covers topics such as cell timing and power modeling;interconnect modeling and analysis, delay calculation, crosstalk, noiseand the chip timing verification using static timing analysis. For eachof these topics, the book provides a theoretical background as well asdetailed examples to elaborate the concepts.

The static timing analysis topics covered start from verification ofsimple blocks useful for a beginner to this field. The topics thenextend to complex nanometer designs with in-depth treatment of conceptssuch as modeling of on-chip variation, clock gating, half-cycle paths,as well as timing of source-synchronous interfaces such as DDR. Theimpact of crosstalk on timing and noise is covered as is the usage ofhierarchical design methodology.

This book addresses CMOS logic gates, cell library, timing arcs,waveform slew, cell capacitance, timing modeling, interconnectparasitics and coupling, pre- and post-layout interconnect modeling,delay calculation, specification of timing constraints for analysis ofinternal paths as well as IO interfaces. Advanced modeling and analysisconcepts such as controlled current source timing and noise models fornanometer technologies, power modeling including active and leakagepower, crosstalk timing and crosstalk glitch calculation, verificationof half-cycle and multi-cycle paths, false paths, synchronousinterfaces are also covered.

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daviehj

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analogmind

多谢楼主

gsy703

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ecnuapple

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aajj

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victorueng

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taohzide

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lalawoo

Thanks ~~

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