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楼主 |
发表于 2006-8-19 14:54:11
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__VectorStart ; Start of ARM processor vectors
LDR pc,ResetV ; 00 - Reset
LDR pc,UndefV ; 04 - Undefined instructions
LDR pc,SWIV ; 08 - SWI instructions
LDR pc,PAbortV ; 0C - Instruction fetch aborts
LDR pc,DAbortV ; 10 - Data access aborts
LDR pc,UnusedV ; 14 - Reserved (was address exception)
LDR pc,IRQV ; 18 - IRQ interrupts
LDR pc,FIQV ; 1C - FIQ interrupts |
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