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Design Verification with e by Samir Palnitkar (English, Chm format)
To find the book at Amazon:
http://www.amazon.com/Design-Verification-e-Samir-Palnitkar/dp/0131413090/ref=sr_1_1?ie=UTF8&s=books&qid=1258394060&sr=1-1
Editorial ReviewsProduct DescriptionE is a new Hardware Verification Language, or HVL. Verification is one of the most time consuming and cumbersome processes in hardware design. Design teams spend 50% to 70% of their time verifying designs, rather than creating new ones. As designs grow more complex, the verification problems increase exponentially - when a design doubles in size, the verification effort can easily quadruple. In the past design teams have used Verilog and VHDL. E gives engineers the speed and efficiency they have been craving, while also allowing for simulation of other components as well. This book emphasizes breadth rather than depth. It imparts to the reader a working knowledge of a broad variety of e-based topics, thus giving the reader a global understanding of e-based design verification. This book should be classified not only as an e book but, more generally, as a design verification book. Due to its popularity, it is likely that e will be standardized in the future.
From the Back CoverDesign Verification with eSamir Palnitkar Written for both experienced and new users, DesignVerification with e gives you a broadcoverage of e. It stresses the practical verification perspective of e rather than emphasizing only itslanguage aspects.
This book—
- Introduces you to e-based verification methodologies
- Describes e syntax in detail, including structs, units, methods, events, temporal expressions. and TCMs
- Explains the concepts of automatic generation, checking and coverage
- Discusses the e Reuse Methodology
- Describes essential topics such as coverage driven verification, e verification components (eVCs), and interfacing with C/C++
- Illustrates a complete verification example in e
- Contains a quick-reference guide to the e language
- Offers many practical verification tips
Includes over 250 illustrations, examples, andexercises, and a verification resource list. Learning objectives and summariesare provided for each chapter.
“Mr. Palnitkar illustrates how and why the power ofthe everification language and the underlying Specman Elite testbench automationtool are used to develop today's most advanced verification environments. Thisbook is valuable to both the novice and the experienced e user. I highlyrecommend it to anyone exploring functional verification” |
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