AMBA axi 问题续

countryhotel

首先谢谢TommyGG 的回答。
今天把AXI协议看完了，有下面问题请各位帮满解决：

Q1：

AHB中M个master与N个slave通过a central multiplexor interconnection scheme（总裁器与译码器等）实现连接通信。在AXI中，master与slave之间有5个channel进行连接（写地址，写数据，写回应，读地址，读数据），这样看似乎是master与slave之间的一一对应关系，但是在AXI标准中又提出interconnect的概念，是否通过interconnect实现M个master与N个slave的互连，如果是，能不能理解为类似AHP中的a central multiplexor interconnection scheme部分，在interconnect内部实现总裁与译码？如果不是，那interconnect的功能是什么？

Q2：
Each AXI channel transfers information in only one direction, and there is no requirement for a fixed relationship between the various channels. This is important because it enables the insertion of a register slice in any channel, at the cost of an additional cycle of latency. This makes possible a trade-off between cycles of latency and maximum frequency of operation.register slice的解释，为什么使用register slice？

countryhotel

Q3：
master的burst transaction中相关控制信息是否走write address channel传输给slave？地址信息为什么为31位，AXI译码方式与AHP中的区别？
Q4：
这里还是需要搞清楚transfer和transaction的区别？注意下面数个描述：“The write address bus gives the address of the first transfer in a write burst transaction.”，“The burst length gives the exact number of transfers in a burst.”，“Every transaction must have the number of transfers specified by ARLEN or AWLEN.”，“The AXI protocol uses burst-based addressing, which means that each transaction consists of a number of data transfers.”我的理解是一次burst可以理解为一个transaction，而在一个transaction内包含burst length个transfer。和TommyGG 的回答是否有冲突？
Q5：
master的burst transaction中相关控制信息是否走write address channel传输给slave？地址信息为什么为31位，AXI译码方式与AHP中的区别？
Q6：
Bufferable与catchable的是什么？具体作用体现？文档中下述描述的解释：
Bufferable (B) bit, ARCACHE[0] and AWCACHE[0]
When this bit is HIGH, it means that the interconnect or any component can delay the transaction reaching its final destination for an arbitrary number of cycles. This is usually only relevant to writes.（延时的作用，什么情况下会出现这种情况？）
Cacheable (C) bit, ARCACHE[1] and AWCACHE[1]
When this bit is HIGH, it means that the transaction at the final destination does not have to match the characteristics of the original transaction.
For writes this means that a number of different writes can be merged together.
For reads this means that a location can be pre-fetched or can be fetched just once for multiple read transactions.（什么情况下读写操作会有这样的需求？）
Q7：
privileged access是指什么样的access（“A privileged processing mode typically has a greater level of access within a system.”）？
secure access与non-secure access的区别，在什么情况下要对access进行这样的标记？
Q8：
Atomic access具体指什么类型操作？
exclusive access与locked access操作的区别是否主要集中在一下描述中：“The exclusive access mechanism enables the implementation of semaphore type operations without requiring the bus to remain locked to a particular master for the duration of the operation. （exclusive access mechanism能完成semaphore type operations，并且在此操作期间不要求当前操作定主机lock总线，semaphore type operations？）The advantage of exclusive access is that semaphore type operations do not impact either the critical bus access latency or the maximum achievable bandwidth.”？
exclusive access怎么翻译, exclusive在什么情况下可以发挥自己的作用？？
semaphore type operations具体指什么类型操作？
A single-ported slave是指什么样的slave，port这里具体指什么？
Q9：
DECERR与SLVERR的区别？
Q10：
在ID tag相同的情况下是怎么样保证有序的？需要保证有序的最小单位是burst还是burst内的transfer？
AWID,WID,ARID RID这几个信号的作用？
Q11：
multiple outstanding addresses是指？
multiple outstanding addresses与transactions out of order是否具有内在联系？
Q12：
the read data reordering depth是指什么？
Q13：
write data interleaving是指什么样的操作？Write data interleaving enables a slave interface to accept interleaved write data with different AWID values. The slave declares a write data interleaving depth that indicates if the interface can accept interleaved write data from sources with different AWID values.
这里的different AWID values是指来自同一master还是不同master？
write data interleaving depth的具体作用？
Q14：
Byte-invariant具体是指什么？能否举一个实例？

hyperpicc

My opinion for Q1: Like OCP-IP, AXI is based on point-to-point mechanism, so it just defines the relationship between a master port and a slave port. Therefore, the 'interconnection' is flexible.

My opinion for Q2: In modern SoCs, because of the complexity, the timing in interconnections becomes critical (because complex combinational paths). The interconnection timing can be 'cut' by using such register-slice techniques.

hyperpicc

My opinion for Q9: DECERR means an error occurs during address decoding. For example, a decoder decodes an invalid address space. SLVERR is from the slave, such like a master attempts to write data to a read-only region.

hyperpicc

My opinion for Q14: For example, some systems with network capabilities, the data endianess may be different from network order, so AXI defines the byte-invariant feature to reduce data-swapping efforts.

chairperson

謝謝回答問題，正好也在學習AXI，受教了。

spatim_tatagad

nice article...regarding axi

royu826

问什么没有人继续回答他的另外的问题了？
请大侠们帮帮忙啊

freud

Q3: 31位哪来的的？
Q4:我理解transaction是burst，transfer是beat
Q6：cachalbe和 bufferable的概念比较复杂，具体可以看看ARM cache相关文档。简单说，这两个概念都是围绕master访问的slave的请求来说的。例如该请求时cacheable的写话，那么实际的写数据不一定更新了主存内容，可以只更新了cache，以后再通过write back方式更新；bufferable也类似，如果是写，那么写数据响应返回给master时，实际写数据不一定到达了slave设备。这个写数据可能被buffer了，而时间未知。如果不是bufferable则写响应反映了slave
实际接收到数据的时刻。说的比较笼统，具体可以参考相应文档。

freud

Q8：原子操作。一般用在多核共享memory的场合。可参考MESI协议。
Q10：ID相同的操作不能够乱序，按beat进行，否则不能区分。
AWID与WID，BID绑定一致,ARID和RID绑定一致，分别用来识别写地址信息、写数据信息和写响应一致，读地址请求和读返回数据一致。