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发表于 2010-12-24 17:56:12
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Explanation in English:
(though in English, has all the details you want to know. Please bear with me. ...
During the layout, a jump using higher interconnect layer means to to cut the length of lower (interconnect) layer down to multiple segments. In that case, the interconnect area of lower layer / gate oxide area will be reduced (minimized), therefore no more rule violation.
For instance, the original layout has poly interconnect of 300 um x 0.6 um, and the thin oxide area is 0.18 um x 0.6 um. It is likely to cause rule violation (of antenna effect) in Area_poly / Area_tox. Break the poly interconnect as early as possible, say break it when it only wires out the gate by 10 um long, and jump up to M1, jump back to poly to continue the rest of the 290-um length, then connect it to a circuit output node. (Remember the next 290-um poly connects to diode junction, so does not cause antenna rule violation. So the rest 290-um poly does not cause antennal rule violation.) During the process step of poly, the "antenna" only consists of 10 um x 0.6 um poly area, instead of 300 um x 0.6 um area. This is why jumping up to higher interconnect layer helps resolve the antenna rule violation. In case, Area of (M1 + poly) / area of tox still causes rule violation, break M1 (to multiple segments), and connect the route by M2, M1 and poly. While processing M1, the antenna only consists of short M1 + short poly. Thus the issue of rule violation is resolved.
By induction, the resolution of antenna rule violation can be derived to "jumping to higher interconnect layer (as early as possible), all the way up to the top (metal) and jumping back down to where the antenna rule violation layer is." |
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