jssc的pll最新文章

海之子306916

1.

A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution Lee, M.; Heidari, M. E.; Abidi, A. A.; Solid-State Circuits, IEEE Journal of Volume 44,  Issue 10,  Oct. 2009 Page(s):2808 - 2816 Digital Object Identifier 10.1109/JSSC.2009.2028753 Summary: This paper presents the design of a digital PLL which uses a high-resolution time-to-digital converter (TDC) for wide loop bandwidth. The TDC uses a time amplification technique to reduce the quantization noise down to less than 1 ps root mean.....

2.

An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

	3.	A Wideband PLL-Based G/FSK Transmitter in 0.18 $mu$m CMOS Tsung-Hsien Lin; Yao-Hong Liu; Solid-State Circuits, IEEE Journal of Volume 44,  Issue 9,  Sept. 2009 Page(s):2452 - 2462 Digital Object Identifier 10.1109/JSSC.2009.2022994 Summary: A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PL.....
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		AbstractPlus | Full Text: PDF(2447 KB)    IEEE JNL

4.

Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages

NANHU_BRUCE

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NANHU_BRUCE

英文版本的吗？

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christing

2# NANHU_BRUCE
还有中文的?

359705716

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fixit

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鋒鋒

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鋒鋒

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鋒鋒

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