猎头职位-上海-前端，后端，RF工程师招聘

fancyflora

Senior Physical Design Engineer
JD:BS/MS in EE/CS required.
Three or more years of hands-on experience in IC physical design, verification and tapeouts.
Proven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation..
Knowledge of Mentor’s Calibre or Synopsys’ Hercules runsets or ruledecks creation and debugging.
Good programming skill. Capable of writing Tcl or Perl.
Familiar with synthesis, static timing analysis.
In-depth understanding of fabrication processing steps used in major fabrication industries.
Self-motivated team worker, good verbal and written communication skills in English.
Technical and team leadership proffered. Previous management experience highly desired.
Experience with synthesis, DFT, and verification is preferred.

Manager Design
JD:Manager, Design
Job Title: Manager, Design
Location: Shanghai
Report to: Director located in US
Job Responsibility:
This position is in a leading edge fast growing US semiconductor company. As a local Design Manager, the individual will have the opportunity to build your local team for IP development and verification. The individual will lead the projects execution, and work closely with other product teams on ARM based embedded SoC products.
Responsibilities include:
1. Build, grow and manage a local team to work closely with US locations.
2. Work with architecture team to understand specification, define and execute the projects.
3. Verilog entry, Logic simulations, synthesis, linting, timing, silicon bring-up.
4. Work with FPGA/Emulation team to perform pre-silicon validation/debug at IP, full-chip and system levels, fullchip integration, and Silicon debug.
5. Documentation
6. Interface with software and integration team
Qualification:
1. MSEE with 6 years of ASIC design and verification experience, with at least 2 years of management experience. PHD is a plus.
2. Experienced with IP design and verification.
3. Hand-on experience with standard design flow and tools on various design phases, including documentation, coding, lint, version control and RTL/gate simulation.
4. Strong team building skill is required
5. Experience with SystemVerilog and VMM is a plus.
6. Must be able to communicate in both written and spoken English.
7. Good team work spirit and communication skill.
8. Strong leadership and problem solving skills

RF AE暂时没JD。
上海张江科创园，猎头职位，急聘~！！
有兴趣的请发简历至：florafang.furui@gmail.com
MSN咨询:fancyflora@live.cn

fancyflora

后端需要多个candidate，帮忙推荐推荐·~~

IC1234

大专学历，版图三年可以吗？

fancyflora

ASIC manager prefer: 有国外工作或教育背景，硅谷公司出来。

RF AE职位全英文面试，大家好好准备，本周见完，继续推荐！