Tutorials on ADCs and DACs By Walt Kester Analog Devices 2006

hbchens

Tutorials on ADC’s and DAC’s

By
Walt Kester Analog Devices 2006

Table of Contents

1
MT-001: Taking the Mystery out of the Infamous Formula,
"SNR=6.02N + 1.76dB," and Why You Should Care
6

1.1
INTRODUCTION
6

1.2
DERIVATION
6

1.3
CORRELATION BETWEEN QUANTIZATION NOISE AND INPUT SIGNAL YIELDS MISLEADING RESULTS
11

1.4
THEORETICAL NOISE FLOOR OF THE FFT OUTPUT
12

1.5
REFERENCES
13

2
MT-002: What the Nyquist Criterion Means to Your Sampled Data System Design
14

2.1
INTRODUCTION
14

2.2
THE NEED FOR A SAMPLE-AND-HOLD AMPLIFIER (SHA) FUNCTION
15

2.3
THE NYQUIST CRITERION
18

2.4
BASEBAND ANTIALIASING FILTERS
20

2.5
UNDERSAMPLING (HARMONIC SAMPLING, BANDPASS SAMPLING, IF SAMPLING, DIRECT IF-TO-DIGITAL CONVERSION)
23

2.6
ANTIALIASING FILTERS IN UNDERSAMPLING APPLICATIONS
24

2.7
SUMMARY
26

2.8
REFERENCES
26

3
MT-003: Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so You Don't Get Lost in the Noise Floor
26

3.1
INTRODUCTION
26

3.2
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD), SIGNAL-TO-NOISE RATIO (SNR), AND EFFECTIVE NUMBER OF BITS (ENOB)
30

3.3
THE MATHEMATICAL RELATIONSHIPS BETWEEN SINAD, SNR, AND THD
32

3.4
SUMMARY
33

3.5
REFERENCES
33

4
MT-004: The Good, the Bad, and the Ugly Aspects of ADC Input Noise –Is No Noise Good Noise?
33

4.1
INTRODUCTION
34

4.2
INPUT-REFERRED NOISE (CODE TRANSITION NOISE)
34

4.3
NOISE-FREE (FLICKER-FREE) CODE RESOLUTION
36

4.4
INCREASING ADC "RESOLUTION" AND REDUCING NOISE BY DIGITAL AVERAGING
37

4.5
DON'T CONFUSE EFFECTIVE NUMBER OF BITS (ENOB) WITH "EFFECTIVE RESOLUTION" OR "NOISE-FREE CODE RESOLUTION"
38

4.6
USING NOISE DITHER TO INCREASE ADC SPURIOUS FREE DYNAMIC RANGE
38

4.7
SUMMARY
43

4.8
ACKNOWLEDGEMENTS
44

4.9
REFERENCES
44

5
MT-005: Noise Power Ratio (NPR) – A 65-Year Old Telephone System Specification Finds New Life in Modern Wireless Applications
44

5.1
INTRODUCTION
44

5.2
HISTORY OF NPR
45

5.3
SUMMARY
53

5.4
REFERENCES
54

5.5
APPENDIX
54

6
MT-006: ADC Noise Figure – An Often Misunderstood and Misinterpreted Specification
56

6.1
INTRODUCTION
57

6.2
ADC NOISE FIGURE DEFINITION
57

6.3
ADC NOISE FIGURE DERIVATION
58

6.4
EXAMPLE CALCULATION FOR AD9446 16-BIT 80/100-MSPS ADC
61

6.5
USING RF TRANSFORMERS TO DECREASE ADC NOISE FIGURE
62

6.6
CASCADED NOISE FIGURE
63

6.7
SUMMARY
65

6.8
REFERENCES
65

7
MT-007: Aperture Time, Aperture Jitter, Aperture Delay Time – Removing the Confusion
65

7.1
INTRODUCTION
66

7.2
EFFECT OF APERTURE JITTER AND SAMPLING CLOCK JITTER ON ADC SIGNAL-TO-NOISE RATIO (SNR)
68

7.3
MEASURING ADC APERTURE JITTER USING FFT TECHNIQUES
70

7.4
SUMMARY
72

7.5
REFERENCES
72

8.... MT-008: Converting Oscillator Phase Noise to Time Jitter
72

8.1
INTRODUCTION
73

8.2
PHASE NOISE DEFINED
73

8.3
CONVERTING PHASE NOISE TO JITTER
76

8.4
REFERENCES
82

9.... MT-009: Data Converter Codes–Can You Decode Them?
83

9.1
INTRODUCTION
83

9.2
UNIPOLAR CODES
86

9.3
GRAY CODE
89

9.4
BIPOLAR CODES
90

9.5
COMPLEMENTARY CODES
94

9.6
ACKNOWLEDGEMENT
94

9.7
REFERENCES
94

10
MT-010: The Importance of Data Converter Static Specifications –Don't Lose Sight of the Basics!
95

10.1
INTRODUCTION
95

10.2
DATA CONVERTER RESOLUTION AND QUANTIZATION
96

10.3
TRANSFER FUNCTIONS OF IDEAL DATA CONVERTERS
96

10.4
DATA CONVERTER GAIN AND OFFSET ERRORS
98

10.5
DATA CONVERTER LINEARITY ERRORS
99

11.. MT-011: Find Those Elusive ADC Sparkle Codes and Metastable States
105

11.1
INTRODUCTION
106

11.2
SPARKLE CODES, ERROR CODES, RABBITS, OR FLYERS
106

11.3
SPARKLE CODES IN FLASH CONVERTERS
107

11.4
SUMMARY
114

11.5
REFERENCES
114

12.. MT-012: Intermodulation Distortion Considerations for ADCs
115

12.1
INTRODUCTION
115

12.2
TWO TONE INTERMODULATION DISTORTION (IMD)
115

12.3
SECOND AND THIRD-ORDER INTERCEPT POINTS (IP2, IP3), 1-dB COMPRESSION POINT
116

12.4
MULTI-TONE SPURIOUS FREE DYAMIC RANGE
119

12.5
SUMMARY
120

12.6
REFERENCES
121

13.. MT-020: ADC Architectures I: The Flash Converter
121

13.1
INTRODUCTION
121

13.2
THE COMPARATOR: A 1-BIT ADC
121

13.3
FLASH CONVERTERS
125

13.4
Figure 4: 3-bit All-Parallel (Flash) Converter
126

13.5
TYPICAL FLASH CONVERTER TIMING
127

13.6
SUMMARY
136

13.7
REFERENCES
137

14.. MT-021: ADC Architectures II: Successive Approximation ADCs
138

14.1
INTRODUCTION
139

14.2
SAR ADC TIMING
140

14.3
ANALOG DEVICES ENTERS THE DATA CONVERTER ARENA IN 1969
145

14.4
Figure 6: ADC-12U 12-Bit, 10-µs SAR ADC from Pastoriza Division of Analog Devices, 1969
146

14.5
MODERN SAR ADCs
148

14.6
PROCESSING INDUSTRIAL-LEVEL SIGNALS
149

14.7
SUMMARY
151

14.8
REFERENCES
151

15.. MT-022: ADC Architectures III: Sigma-Delta ADC Basics
152

15.1
INTRODUCTION
153

15.2
HISTORICAL PERSPECTIVE
153

15.3
BASICS OF Σ-Δ ADCS
156

15.4
FREQUENCY DOMAIN ANALYSIS OF A SIGMA-DELTA ADC AND NOISE SHAPING
160

15.5
SUMMARY
164

15.6
REFERENCES
164

16.. MT-023: ADC Architectures IV: Sigma-Delta ADC Advanced Concepts and Applications
166

16.1
INTRODUCTION
167

16.2
IDLE TONE CONSIDERATIONS
167

16.3
HIGHER ORDER LOOP CONSIDERATIONS
169

16.4
MULTI-BIT SIGMA-DELTA CONVERTERS
169

16.5
DIGITAL FILTER IMPLICATIONS ON MULTIPLEXED APPLICATIONS
172

16.6
MULTISTAGE NOISE SHAPING (MASH) SIGMA-DELTA CONVERTERS
173

16.7
HIGH RESOLUTION MEASUREMENT SIGMA-DELTA ADCS
174

16.8
BANDPASS SIGMA-DELTA CONVERTERS
176

16.9
SUMMARY
177

16.10
REFERENCES
177

17.. MT-024: ADC Architectures V: Pipelined Subranging ADCs
178

17.1
INTRODUCTION
178

17.2
BASIC SUBRANGING ADC ARCHITECTURE
179

17.3
SUBRANGING ADCs WITH DIGITAL ERROR CORRECTION
182

17.4
Figure 6: A 6-Bit Subranging Error Corrected ADC, N1 = 3, N2 = 4
184

17.5
PIPELINED SUBRANGING ADCs INCREASE SPEED
187

17.6
RECIRCULATING SUBRANGING PIPELINED ADC
190

17.7
MODERN MONOLITHIC PIPELINED ADCs FOR VIDEO AND IMAGE PROCESSING
191

17.8
PIPELINED ADCs FOR WIDEBAND COMMUNICATIONS
191

17.9
THE LATEST IN PIPELINED ADCs
193

17.10
SUMMARY
193

17.11
REFERENCES
194

18.. MT-025: ADC Architectures VI: Folding ADCs
195

18.1
INTRODUCTION
195

18.2
BINARY AND FOLDING BIT-PER-STAGE (SERIAL) ADCs
196

18.3
SUMMARY
206

18.4
REFERENCES
206

19.. MT-026: ADC Architectures VII: Counting ADCs
208

19.1
INTRODUCTION
208

19.2
A. H. REEVES' 5-BIT COUNTING ADC
208

19.3
CHARGE RUN-DOWN ADC
209

19.4
RAMP RUN-UP ADC
210

19.5
TRACKING ADC
211

19.6
REFERENCES
213

20.. MT-027: ADC Architectures VIII: Integrating ADCs
214

20.1
INTRODUCTION
214

20.2
MULTI-SLOPE ADCs
214

20.3
REFERENCES
216

21.. MT-029: Optical Encoders
218

22
MT-031: Grounding Data Converters and Solving the Mystery of "AGND" and "DGND"
220

22.1
INTRODUCTION
220

22.2
GROUND AND POWER PLANES
221

22.3
LOW AND HIGH FREQUENCY DECOUPLING
222

22.4
DOUBLE-SIDED VS. MULTILAYER PRINTED CIRCUIT BOARDS
223

22.5
MULTICARD MIXED-SIGNALS SYSTEMS
224

22.6
SEPARATING ANALOG AND DIGITAL GROUND PLANES
225

22.7
GROUNDING AND DECOUPLING MIXED-SIGNAL ICs WITH LOW DIGITAL CURRENTS
226

22.8
TREAT THE ADC DIGITAL OUTPUTS WITH CARE
228

22.9
SAMPLING CLOCK CONSIDERATIONS
230

22.10
THE ORIGINS OF THE CONFUSION ABOUT MIXED-SIGNAL GROUNDING: APPLYING SINGLE-CARD GROUNDING CONCEPTS TO MULTICARD SYSTEMS
231

22.11
SUMMARY:
GROUNDING MIXED SIGNAL DEVICES WITH LOW DIGITAL CURRENTS IN A MULTICARD SYSTEM
232

22.12
SUMMARY:
GROUNDING MIXED SIGNAL DEVICES WITH HIGH DIGITAL CURRENTS IN A MULTICARD SYSTEM (USE THIS METHOD WITH CAUTION!)
234

22.13
GROUNDING SUMMARY
235

22.14
SOME GENERAL PC BOARD LAYOUT GUIDELINES FOR MIXED-SIGNAL SYSTEMS
235

22.15
REFERENCES
237

herrgeothe

顶啊。。。。。顶啊。。。。。。好东西。。。。。指导性的。谢谢楼主

herrgeothe

:Q 感觉像骗子，付了5信元还是没有下载到。。。。鄙视之

surer

dingdingding

hbchens

原帖由 herrgeothe 于 2009-5-2 23:09 发表

                               
登录/注册后可看大图

:Q 感觉像骗子，付了5信元还是没有下载到。。。。鄙视之

大哥，看完之后您再发表评论～～

sendoh2008

看看卡看，这么好的东东

s2618017

評價兩極~~
下載來研究一下
感恩ㄟ!!

swolftam

thank you!

swolftam

thank you

vulcan_989

怎么没有DAC的？